component
W25Q32JVSSIQ
Public Made by Adomby adom
Winbond Elec NOR FLASH, SOIC-8-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
0370cc6
1mo ago
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{
"schema": "adom.pads/1",
"slug": "w25q32jvssiq",
"footprint": "SOIC-8_3.9x4.9mm_P1.27mm",
"generated_from": {
"footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"pins": "page.json:component.pins",
"overrides": null
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"
},
"pad_count": 8,
"symbol_pins": [
"1",
"2",
"3",
"4",
"5",
"6",
"7",
"8"
],
"paste_apertures": 0,
"issues": [],
"pads": [
{
"pad": "1",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "1",
"name": "/CS",
"type": "input",
"description": "SPI Chip Select input, active low. Drive low to select the device and clock instructions/data on DI/DO or IO0-IO3; drive high to deselect and place I/O pins in high impedance. Requires a valid high-to-low transition after power-up before any instruction is accepted; a pull-up to VCC is recommended.",
"is_pin1": true,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "2",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "2",
"name": "DO/IO1",
"type": "bidirectional",
"description": "Standard/Dual SPI serial data output (DO) driven on the falling edge of CLK. In Quad SPI mode (Quad Enable QE=1) this pin becomes bidirectional IO1 for both write and read transfers.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "3",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "3",
"name": "/WP/IO2",
"type": "bidirectional",
"description": "Active-low Write Protect input in standard/Dual SPI mode; when asserted together with the SRP/BP/TB/SEC/CMP bits it hardware-protects part or all of the array and the Status Register. In Quad SPI mode (QE=1) this pin becomes bidirectional IO2.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "4",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "4",
"name": "GND",
"type": "power_in",
"description": "Device ground reference. Connect to the system 0 V/GND plane.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "5",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "5",
"name": "DI/IO0",
"type": "bidirectional",
"description": "Standard/Dual SPI serial data input (DI), sampled on the rising edge of CLK for instructions, addresses and data. In Quad SPI mode this pin becomes bidirectional IO0.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "6",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "6",
"name": "CLK",
"type": "input",
"description": "SPI serial clock input. Provides the timing reference for all serial input and output operations; supports up to 133 MHz. Data on DI/IOx is latched on the rising edge; DO/IOx is updated on the falling edge.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "7",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "7",
"name": "/HOLD/IO3",
"type": "bidirectional",
"description": "Active-low /HOLD input in standard/Dual SPI mode: while /CS is low, driving /HOLD low pauses the device (DO goes high-Z, DI/CLK are ignored) without deselecting it. In Quad SPI mode (QE=1) the pin is repurposed as bidirectional IO3. Note: on this 8-pin package the pin does NOT provide the dedicated hardware /RESET function (only SOIC-16 and TFBGA packages expose /RESET).",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "8",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "8",
"name": "VCC",
"type": "power_in",
"description": "Core and I/O supply, 2.7 V to 3.6 V. Decouple with a local ceramic bypass capacitor close to the pin.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
}
]
}