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W25Q32JVSNIQ

Public Made by Adom

by adom

WINBOND Global Sourcing Parts, SOIC-8-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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W25Q32JVSNIQ

WINBOND · Global Sourcing Parts · SOIC-8-150mil

W25Q32JVSNIQ from WINBOND, in a SOIC-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /CS input Chip Select Input: when high the device is deselected and DO is high impedance, and /CS must track the VCC supply level at power-up and power-down.
2 DO (IO1) bidirectional Data Output (Data Input Output 1), used for Standard SPI read data and as IO1 for Dual and QPI operation; data is read on the falling edge of CLK.
3 /WP (IO2) bidirectional Write Protect Input (Data Input Output 2), active low, used with the Status Register protect bits; it becomes IO2 when QE=1 and then the write-protect function is unavailable.
4 GND power_in Ground.
5 DI (IO0) bidirectional Data Input (Data Input Output 0), used for serial instruction, address and data input on the rising edge of CLK, and as IO0 for Dual and Quad operation.
6 CLK input Serial Clock Input providing timing for serial input and output operations.
7 /HOLD or /RESET (IO3) bidirectional Hold or Reset Input (Data Input Output 3): active-low /HOLD pauses the device while /CS is low, or /RESET when HOLD/RST=1 and QE=0, and it becomes IO3 when QE=1.
8 VCC power_in Power Supply, 2.7V to 3.6V per the operating range.

Key specifications

Parameter Value
Manufacturer WINBOND
Package SOIC-8-150mil
Category Global Sourcing Parts
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (FR=133MHz, fR=50MHz) VCC 3 3.6 V FR = 133MHz, fR = 50MHz 86
Supply Voltage (FR=104MHz, fR=50MHz) VCC 2.7 3 V FR = 104MHz, fR = 50MHz 86
Ambient Temperature, Operating (Industrial) TA -40 85 °C Industrial (grade I) 86
Supply Voltage (absolute maximum) VCC -0.6 4.6 V 86
Voltage Applied to Any Pin (relative to ground) VIO -0.6 V Relative to ground; upper limit printed as VCC+0.4 86
Storage Temperature TSTG -65 150 °C 86
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model 86
VCC (min) to /CS Low tVSL 20 µs Characterized only 87
Time Delay Before Write Instruction tPUW 5 ms Characterized only 87
Write Inhibit Threshold Voltage VWI 1 2 V Characterized only 87
Input Capacitance CIN 6 pF VIN = 0V; tested on sample basis, TA = 25°C, VCC = 3.0V 88
Output Capacitance Cout 8 pF VOUT = 0V; tested on sample basis, TA = 25°C, VCC = 3.0V 88
Input Leakage ILI -2 2 µA 88
I/O Leakage ILO -2 2 µA 88
Standby Current ICC1 10 50 µA /CS = VCC, VIN = GND or VCC 88
Power-down Current ICC2 1 15 µA /CS = VCC, VIN = GND or VCC 88
Current Read Data / Dual / Quad 50MHz ICC3 8 15 mA C = 0.1 VCC / 0.9 VCC, DO = Open; checker board pattern 88
Current Read Data / Dual / Quad 80MHz ICC3 10 18 mA C = 0.1 VCC / 0.9 VCC, DO = Open; checker board pattern 88
Current Read Data / Dual / Quad 104MHz ICC3 12 20 mA C = 0.1 VCC / 0.9 VCC, DO = Open; checker board pattern 88
Current Write Status Register ICC4 20 25 mA /CS = VCC 88
Current Page Program ICC5 20 25 mA /CS = VCC 88
Current Sector/Block Erase ICC6 20 25 mA /CS = VCC 88
Current Chip Erase ICC7 20 25 mA /CS = VCC 88
Input Low Voltage VIL -0.5 0.3 x VCC Printed as VCC x 0.3 (max); min printed as -0.5 V 88
Input High Voltage VIH 0.7 0.4 x VCC Printed as VCC x 0.7 (min) and VCC + 0.4 V (max; 0.4 is the V added to VCC) 88
Output Low Voltage VOL 0.2 V IOL = 100 µA 88
Output High Voltage VOH -0.2 V offset from VCC IOH = -100 µA; printed as VCC, 0.2 88
Clock frequency for SPI & QPI instructions (3.0V-3.6V) FR 133 MHz Except Read Data (03h) & DTR instructions; min printed as D.C. 90
Clock frequency for SPI & QPI instructions (2.7V-3.0V) FR 104 MHz Except Read Data (03h) & DTR instructions; min printed as D.C. 90
Clock frequency DTR instructions (3.0V-3.6V) FR 66 MHz min printed as D.C. 90
Clock frequency DTR instructions (2.7V-3.0V) FR 52 MHz min printed as D.C. 90
Clock frequency for Read Data instruction (03h) fR 50 MHz min printed as D.C. 90
Clock High, Low Time (all instructions except Read Data) tCLH, tCLL 45 %Pc Pc = 1/fC(MAX) 90
/CS Active Setup Time relative to CLK tSLCH 3 ns 90
/CS Not Active Hold Time relative to CLK tCHSL 3 ns 90
Data In Setup Time tDVCH 1 ns 90
Data In Hold Time tCHDX 2 ns 90
/CS Deselect Time (for Read) tSHSL1 10 ns 90
/CS Deselect Time (for Erase or Program or Write) tSHSL2 50 ns 90
Output Disable Time tSHQZ 7 ns Value guaranteed by design/characterization 90
Clock Low to Output Valid tCLQV 6 ns 90
Output Hold Time tCLQX 1.5 ns 90
/HOLD Active Setup Time relative to CLK tHLCH 5 ns 90
/HOLD Active Hold Time relative to CLK tCHHH 5 ns 90
/HOLD to Output High-Z tHHQX 7 ns Printed as /HOLD to Output Low-Z (tLZ) 91
/HOLD to Output High-Z tHLQZ 12 ns 91
Write Protect Setup Time Before /CS Low tWHSL 20 ns 91
Write Protect Hold Time After /CS High tSHWL 100 ns 91
/CS High to Power-down Mode tDP 3 µs 91
/CS High to Standby Mode without ID Read tRES1 3 µs 91
/CS High to Standby Mode with ID Read tRES2 1.8 µs 91
/CS High to next Instruction after Suspend tSUS 20 µs 91
/CS High to next Instruction after Reset tRST 30 µs 91
/RESET pin Low period to reset the device tRESET 1 µs Shorter pulse possible (few hundred ns); 1 µs minimum recommended 91
Write Status Register Time tW 10 15 ms 91
Page Program Time tPP 0.4 3 ms 91
Sector Erase Time (4KB) tSE 45 400 ms 91
Block Erase Time (32KB) tBE1 120 1600 ms 91
Block Erase Time (64KB) tBE2 150 2000 ms 91
Chip Erase Time tCE 10 50 s 91

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 10.1 8-Pin SOIC 150-mil (Package Code SN) ...........................................................................92 10.3 8-Pin SOIC 208-mil (Package Code SS)....................................... 4

CAD (KiCad official)

  • Symbol: W25Q32JVSNIQ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-150mil (KiCad packages3D, STEP)
  • 3D model files: w25q32jvsniq-etched.step / w25q32jvsniq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w25q32jvsniq.step / w25q32jvsniq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WINBOND datasheet (103 pp, sha256 edccaf8f0b02c4c4, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF