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W25Q128JVSIM

Public Made by Adom

by adom

Winbond Elec NOR FLASH, SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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W25Q128JVSIM

Winbond Elec · NOR FLASH · SOIC-8-208mil

W25Q128JVSIM from Winbond Elec, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /CS input Chip Select Input; when /CS is high the device is deselected and the DO/IO pins are high impedance, and /CS must track the VCC supply level at power-up and power-down.
2 DO (IO1) bidirectional Data Output (Data Input Output 1); used as the unidirectional DO output for Standard SPI and as bidirectional IO1 for Dual and Quad SPI instructions.
3 /WP (IO2) bidirectional Write Protect Input (Data Input Output 2); active-low pin that protects the Status Register when QE=0, and becomes IO2 for Quad SPI when QE=1 (write protect not available then).
4 GND power_in Ground.
5 DI (IO0) bidirectional Data Input (Data Input Output 0); used as the unidirectional DI input for Standard SPI and as bidirectional IO0 for Dual and Quad SPI instructions.
6 CLK input Serial Clock Input providing the timing for serial input and output operations.
7 /HOLD or /RESET (IO3) bidirectional Hold or Reset Input (Data Input Output 3); /HOLD is active low and pauses the device while selected when QE=0, the pin can be configured as /RESET via HOLD/RST, and it becomes IO3 when QE=1.
8 VCC power_in Power Supply; the device operates from a single 2.7V to 3.6V supply (per the General Descriptions).

Key specifications

Parameter Value
Manufacturer Winbond Elec
Package SOIC-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC -0.6 4.6 V 86
Voltage Applied to Any Pin VIO -0.6 V Relative to Ground 86
Transient Voltage on any Pin VIOT -2 V <20nS Transient, Relative to Ground 86
Storage Temperature TSTG -65 150 °C 86
Electrostatic Discharge Voltage VESD -2000 2000 V Human Body Model 86
Supply Voltage VCC 3 3.6 V FR = 133MHz, fR = 50MHz 86
Supply Voltage VCC 2.7 3 V FR = 104MHz, fR = 50MHz 86
Ambient Temperature, Operating TA -40 85 °C Industrial 86
VCC (min) to /CS Low tVSL 20 µs 87
Time Delay Before Write Instruction tPUW 5 ms 87
Write Inhibit Threshold Voltage VWI 1 2 V 87
Input Capacitance CIN 6 pF VIN = 0V 88
Output Capacitance COUT 8 pF VOUT = 0V 88
Input Leakage ILI -2 2 µA 88
I/O Leakage ILO -2 2 µA 88
Standby Current ICC1 10 60 µA /CS = VCC, VIN = GND or VCC 88
Power-down Current ICC2 1 20 µA /CS = VCC, VIN = GND or VCC 88
Current Read Data / Dual / Quad 50MHz ICC3 8 15 mA C = 0.1 VCC / 0.9 VCC, DO = Open 88
Current Read Data / Dual / Quad 80MHz ICC3 10 18 mA C = 0.1 VCC / 0.9 VCC, DO = Open 88
Current Read Data / Dual / Quad 104MHz ICC3 12 20 mA C = 0.1 VCC / 0.9 VCC, DO = Open 88
Current Write Status Register ICC4 20 25 mA /CS = VCC 88
Current Page Program ICC5 20 25 mA /CS = VCC 88
Current Sector/Block Erase ICC6 20 25 mA /CS = VCC 88
Current Chip Erase ICC7 20 25 mA /CS = VCC 88
Input Low Voltage VIL -0.5 V 88
Output Low Voltage VOL 0.2 V IOL = 100 µA 88
Clock frequency FR, 3.0V-3.6V FR 133 MHz Except Read Data (03h) & DTR instructions 90
Clock frequency FR, 2.7V-3.0V FR 104 MHz Except Read Data (03h) & DTR instructions 90
Clock frequency DTR instructions, 3.0V-3.6V FR 66 MHz DTR instructions 90
Clock frequency DTR instructions, 2.7V-3.0V FR 52 MHz DTR instructions 90
Clock frequency for Read Data instruction fR 50 MHz Read Data (03h) 90
/CS Active Setup Time relative to CLK tSLCH 3 ns 90
/CS Not Active Hold Time relative to CLK tCHSL 3 ns 90
Data In Setup Time tDVCH 1 ns 90
Data In Hold Time tCHDX 2 ns 90
/CS Deselect Time (for Read) tSHSL1 10 ns 90
/CS Deselect Time (for Erase or Program or Write) tSHSL2 50 ns 90
Output Disable Time tSHQZ 7 ns 90
Clock Low to Output Valid tCLQV 6 ns 90
Output Hold Time tCLQX 1.5 ns 90
/HOLD Active Setup Time relative to CLK tHLCH 5 ns 90
/HOLD Active Hold Time relative to CLK tCHHH 5 ns 90
/HOLD to Output Low-Z tHHQX 7 ns 90
/HOLD to Output High-Z tHLQZ 12 ns 90
Write Protect Setup Time Before /CS Low tWHSL 20 ns Only when SRP=1 (Write Status Register) 90
Write Protect Hold Time After /CS High tSHWL 100 ns Only when SRP=1 (Write Status Register) 90
/CS High to Power-down Mode tDP 3 µs 90
/CS High to Standby Mode without ID Read tRES1 3 µs 90
/CS High to Standby Mode with ID Read tRES2 1.8 µs 90
/CS High to next Instruction after Suspend tSUS 20 µs 90
/CS High to next Instruction after Reset tRST 30 µs 90
/RESET pin Low period to reset the device tRESET 1 µs Recommended minimum; shorter may work (footnote 4) 90
Write Status Register Time tW 10 15 ms 90
Page Program Time tPP 0.4 3 ms 90
Sector Erase Time (4KB) tSE 45 400 ms 90
Block Erase Time (32KB) tBE1 120 1600 ms 90
Block Erase Time (64KB) tBE2 150 2000 ms 90
Chip Erase Time tCE 40 200 s 90

CAD (KiCad official)

  • Symbol: W25Q128JVSIM
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
  • 3D model files: w25q128jvsim-etched.step / w25q128jvsim-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); w25q128jvsim.step / w25q128jvsim.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Winbond Elec datasheet (101 pp, sha256 8074d84a409fce4a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF