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Contents

README

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VST011N10MS-G

Vergiga(威兆) · IC · TO-220AB

VST011N10MS-G from Vergiga(威兆), in a TO-220AB. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; gate-source voltage limited to ±20 V with threshold of 1.4 V min to 2.5 V max at 250 µA.
2 D passive Drain (also connected to the tab); 100 V drain-source breakdown voltage and 65 A continuous drain current at TC=25°C.
3 S passive Source; body diode continuous forward current of 65 A at TC=25°C.

Key specifications

Parameter Value
Manufacturer Vergiga(威兆)
Package TO-220AB
Category
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-Source voltage VGS -20 20 V 1
Diode continuous forward current IS 65 A TC=25°C 1
Continuous drain current @VGS=10V ID 65 A TC=25°C 1
Continuous drain current @VGS=10V ID 46 A TC=100°C 1
Pulse drain current tested IDM 260 A TC=25°C 1
Continuous drain current @VGS=10V IDSM 10 A TA=25°C 1
Continuous drain current @VGS=10V IDSM 8 A TA=70°C 1
Avalanche energy, single pulsed EAS 16 mJ Single pulse; starting TJ=25°C, L=0.5mH, RG=25Ω, IAS=8A, VGS=10V (note ②) 1
Maximum power dissipation PD 86 W TC=25°C 1
Maximum power dissipation PDSM 2 W TA=25°C 1
Storage and Junction Temperature Range TSTG,TJ -55 175 °C 1
Thermal Resistance, Junction-to-Case RθJC 1.75 2.1 °C/W 1
Thermal Resistance, Junction-to-Ambient RθJA 62.5 75 °C/W 1
Drain-Source Breakdown Voltage V(BR)DSS 100 V VGS=0V, ID=250μA 2
Zero Gate Voltage Drain Current IDSS 1 μA VDS=100V, VGS=0V 2
Zero Gate Voltage Drain Current (Tj=125℃) IDSS 100 μA Tj=125℃, VDS=100V, VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 2
Gate Threshold Voltage VGS(TH) 1.4 1.8 2.5 V VDS=VGS, ID=250μA 2
Drain-Source On-State Resistance RDS(ON) 10 13 mΩ VGS=10V, ID=40A; pulse width ≤380μs, duty cycle ≤2% (note ④) 2
Drain-Source On-State Resistance RDS(ON) 13.5 18 mΩ VGS=4.5V, ID=25A; pulse width ≤380μs, duty cycle ≤2% (note ④) 2
Input Capacitance Ciss 1145 1525 2030 pF VDS=30V, VGS=0V, f=1MHz 2
Output Capacitance Coss 525 700 930 pF 2
Reverse Transfer Capacitance Crss 23 30 40 pF 2
Gate Resistance Rg 0.2 0.7 1.5 Ω f=1MHz 2
Total Gate Charge (10V) Qg (10V) 25.5 34 nC VDS=50V, ID=40A, VGS=10V 2
Total Gate Charge (4.5V) Qg (4.5V) 13 17 nC 2
Gate-Source Charge Qgs 5.5 7.3 nC 2
Gate-Drain Charge Qgd 5.3 8 nC 2
Forward on voltage VSD 0.9 1.2 V ISD=40A, VGS=0V 2
Reverse Recovery Time trr 40 80 ns Tj=25℃, Isd=40A, VGS=0V, di/dt=100A/μs 2
Reverse Recovery Charge Qrr 32 64 nC 2

CAD (KiCad official)

  • Symbol: VST011N10MS-G
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220AB (KiCad packages3D, STEP)
  • 3D model files: vst011n10ms-g-etched.step / vst011n10ms-g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vst011n10ms-g.step / vst011n10ms-g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vergiga(威兆) datasheet (6 pp, sha256 9b85d304e96b717a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF