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VSP5612RSHR

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Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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VSP5612RSHR

Texas Instruments · Analog Front End (AFE) · VQFN-56(7x7)

VSP5612RSHR from Texas Instruments, in a VQFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TEST input Internal test pin that the datasheet says must be connected to DGND.
2 AVDD_LDO power_out Analog core power voltage output of the 1.8 V LDO that the datasheet says is not connected (left open).
3 VSS power_in LDO and analog I/O ground.
4 AIN1 input First channel analog signal input; if unused it can be left open or decoupled to GND with a decoupling capacitor.
5 AINGND1 power_in First channel analog signal ground; if unused it can be left open or decoupled to GND with a decoupling capacitor.
6 AIN2 input Second channel analog signal input; if unused it can be left open or decoupled to GND with a decoupling capacitor.
7 AINGND2 power_in Second channel analog signal ground; if unused it can be left open or decoupled to GND with a decoupling capacitor.
8 AIN3 input Third channel analog signal input; if unused it can be left open or decoupled to GND with a decoupling capacitor.
9 AINGND3 power_in Third channel analog signal ground; if unused it can be left open or decoupled to GND with a decoupling capacitor.
10 AIN4 input Fourth channel analog signal input; if unused it can be left open or decoupled to GND with a decoupling capacitor.
11 AINGND4 power_in Fourth channel analog signal ground; if unused it can be left open or decoupled to GND with a decoupling capacitor.
12 VSS power_in LDO and analog I/O ground.
13 REF_AIN bidirectional Selects analog reference direction: 0 = analog signal reference output (default), 1 = analog signal reference input.
14 ISET output Internal reference voltage output that must be bypassed to ground with a 10-kΩ ±1% resistor.
15 VSS power_in LDO and analog I/O ground.
16 REFP output Positive reference output that must be bypassed to AGND with a 0.1-µF capacitor.
17 REFN output Negative reference output that must be bypassed to AGND with a 0.1-µF capacitor.
18 VSS power_in LDO and analog I/O ground.
19 VDD power_in LDO and analog I/O power supply; the recommended range is 3.0 V to 3.6 V (3.3 V nominal).
20 XSH1 output Sensor shift gate output 1 (slow transfer clock).
21 XSH2 output Sensor shift gate output 2 (slow transfer clock).
22 XSH3 output Sensor shift gate output 3 (slow transfer clock).
23 XSH4 output Sensor shift gate output 4 (slow transfer clock).
24 GPIO0 bidirectional Selected by GPIO0_SEL: 0 = GPI0 general-purpose input port 0 (default, internal pull-down on input), 1 = GPO0 general-purpose output port 0.
25 SDO/GPIO2 bidirectional Selected by GPIO2_SDO_SEL: 0 = GPI2 (default, internal pull-down on input), 1 = GPO2, 2 = reserved, 3 = SDO serial interface data output.
26 DVSS power_in Digital ground.
27 RCLKN input LVDS clock input (negative); the RCLK clock rate is specified as 1 to 11.66 MHz.
28 RCLKP input CMOS master clock input or positive LVDS clock input; the MCLK frequency is specified as 1 to 11.66 MHz for VSP5610, 1 to 16.66 MHz for VSP5611, and 1 to 23.33 MHz for VSP5612.
29 DVSS power_in Digital ground.
30 SEN input Serial interface enable, active low, with an internal pull-up resistor.
31 SDI bidirectional Selected by SDI_BUFF_CTRL: 0 = serial interface data input, 1 = serial interface data input/output with internal pull-down resistor.
32 SCLK input Serial interface clock with an internal pull-down resistor; the serial I/O clock frequency is specified as up to 10 MHz.
33 TCLK-/CK1/D7 output Negative LVDS clock output, clock output 1, or data output bit 7 (LVDS, 3.3 V).
34 TCLK+/CK0/D6 output Positive LVDS clock output, clock output 0, or data output bit 6 (LVDS, 3.3 V).
35 TC-/D5 output Negative TC channel LVDS data output or data output bit 5 (3.3 V LVDS).
36 TC+/D4 output Positive TC channel LVDS data output or data output bit 4 (3.3 V LVDS).
37 TB-/D3 output Negative TB channel LVDS data output or data output bit 3 (3.3 V LVDS).
38 TB+/D2 output Positive TB channel LVDS data output or data output bit 2 (3.3 V LVDS).
39 TA-/D1 output Negative TA channel LVDS data output or data output bit 1 (3.3 V LVDS).
40 TA+/D0 output Positive TA channel LVDS data output or data output bit 0 (3.3 V LVDS).
41 LVDD power_in LVDS/CMOS output power supply; the recommended range is 3.0 V to 3.6 V (3.3 V nominal).
42 LVSS power_in LVDS/CMOS output ground.
43 DVDD_IO power_in Digital I/O power supply; the recommended range is 3.0 V to 3.6 V (3.3 V nominal).
44 DVSS power_in Digital ground.
45 XLSYNC bidirectional Selected by XLSYNC_SEL: 0 = internal line synchronous signal output (default), 1 = external line synchronous signal input with polarity set by XLSYNC_POL (default active high); internal pull-down on input.
46 SDO/GPIO1 bidirectional Selected by GPIO1_SDO_SEL: 0 = GPI1 (default, internal pull-down on input), 1 = GPO1, 2 = reserved internal test input, 3 = SDO serial interface data output.
47 XST/GPIO3 bidirectional Selected by GPIO3_XST_SEL: 0 = GPI3 (default, internal pull-down on input), 1 = GPO3, 2 = reserved internal test input, 3 = XST storage pulse output.
48 XCLR output Sensor clear gate output.
49 XP1 output Fast transfer clock output φ1.
50 XP2 output Fast transfer clock output φ2.
51 XP3 output Fast transfer clock output φ3.
52 XP4 output Fast transfer clock output φ4.
53 X1L output Fast transfer clock output 1L.
54 X2L output Fast transfer clock output 2L.
55 XCP output Clamp gate clock output.
56 XRS output Reset gate clock output.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-56(7x7)
Category Data Acquisition
Pins 57

CAD (KiCad official)

  • Symbol: VSP5612RSHR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56(7x7) (KiCad packages3D, STEP)
  • 3D model files: vsp5612rshr-etched.step / vsp5612rshr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsp5612rshr.step / vsp5612rshr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 b01183c0d2c944e8, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF