component
VSP5610RSHR
Public Made by Adomby adom
Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
12 files changed
+20430
docs/hero.pngadded⋯ 1 unchanged line ⋯
docs/vsp5610rshr-datasheet.pdfadded⋯ 1 unchanged line ⋯
package.jsonadded+448@@ -0,0 +1,448 @@+{+ "slug": "vsp5610rshr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "vsp5610rshr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "vsp5610rshr.kicad_sym",+ "vsp5610rshr.kicad_mod",+ "vsp5610rshr.glb",+ "vsp5610rshr.step",+ "vsp5610rshr.lbr",+ "docs/hero.png",+ "docs/vsp5610rshr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "vsp5610rshr-hero.glb",+ "vsp5610rshr-hero.overlay.json"+ ],+ "component": {+ "mpn": "VSP5610RSHR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-56(7x7)",+ "pin_count": 57,+ "category": "Data Acquisition",+ "subcategory": "Analog Front End (AFE)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/vsp5612",+ "parts": {+ "symbol": "vsp5610rshr.kicad_sym",+ "footprint": "vsp5610rshr.kicad_mod",+ "model_3d": "vsp5610rshr-hero.glb",+ "model_3d_plain": "vsp5610rshr.glb",+ "model_3d_step": "vsp5610rshr-etched.step",+ "model_3d_step_plain": "vsp5610rshr.step",+ "lbr": "vsp5610rshr.lbr"+ },+ "distributor_links": {+ "lcsc": 2651566,+ "digikey": "296-29456-2-ND",+ "mouser": "595-VSP5610RSHR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T20:10:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-29456-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-VSP5610RSHR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TEST",+ "type": "input",+ "description": "Internal test pin; connect to DGND"+ },+ {+ "number": "2",+ "name": "AVDD_LDO",+ "type": "power_out",+ "description": "Analog core power voltage output; not connected, open"+ },+ {+ "number": "3",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "4",+ "name": "AIN1",+ "type": "input",+ "description": "First channel analog signal input"+ },+ {+ "number": "5",+ "name": "AINGND1",+ "type": "power_in",+ "description": "First channel analog signal ground"+ },+ {+ "number": "6",+ "name": "AIN2",+ "type": "input",+ "description": "Second channel analog signal input"+ },+ {+ "number": "7",+ "name": "AINGND2",+ "type": "power_in",+ "description": "Second channel analog signal ground"+ },+ {+ "number": "8",+ "name": "AIN3",+ "type": "input",+ "description": "Third channel analog signal input"+ },+ {+ "number": "9",+ "name": "AINGND3",+ "type": "power_in",+ "description": "Third channel analog signal ground"+ },+ {+ "number": "10",+ "name": "AIN4",+ "type": "input",+ "description": "Fourth channel analog signal input"+ },+ {+ "number": "11",+ "name": "AINGND4",+ "type": "power_in",+ "description": "Fourth channel analog signal ground"+ },+ {+ "number": "12",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "13",+ "name": "REF_AIN",+ "type": "bidirectional",+ "description": "Analog signal reference output (default) or analog signal reference input"+ },+ {+ "number": "14",+ "name": "ISET",+ "type": "output",+ "description": "Internal reference voltage output; bypass to ground with a 10-kΩ ±1% resistor"+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "16",+ "name": "REFP",+ "type": "output",+ "description": "Positive reference; bypass to AGND with a 0.1-μF capacitor"+ },+ {+ "number": "17",+ "name": "REFN",+ "type": "output",+ "description": "Negative reference; bypass to AGND with a 0.1-μF capacitor"+ },+ {+ "number": "18",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "19",+ "name": "VDD",+ "type": "power_in",+ "description": "LDO and analog I/O power supply"+ },+ {+ "number": "20",+ "name": "XSH1",+ "type": "output",+ "description": "Sensor shift gate output 1"+ },+ {+ "number": "21",+ "name": "XSH2",+ "type": "output",+ "description": "Sensor shift gate output 2"+ },+ {+ "number": "22",+ "name": "XSH3",+ "type": "output",+ "description": "Sensor shift gate output 3"+ },+ {+ "number": "23",+ "name": "XSH4",+ "type": "output",+ "description": "Sensor shift gate output 4"+ },+ {+ "number": "24",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose input port 0 (default, with internal pull-down) or general-purpose output port 0"+ },+ {+ "number": "25",+ "name": "SDO/GPIO2",+ "type": "bidirectional",+ "description": "General-purpose input port 2 (default, with internal pull-down), general-purpose output port 2, or serial I/F data output"+ },+ {+ "number": "26",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "27",+ "name": "RCLKN",+ "type": "input",+ "description": "LVDS clock input"+ },+ {+ "number": "28",+ "name": "RCLKP",+ "type": "input",+ "description": "CMOS master clock input or positive LVDS clock input"+ },+ {+ "number": "29",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "30",+ "name": "SEN",+ "type": "input",+ "description": "Serial I/F enable; active low with internal pull-up resistor"+ },+ {+ "number": "31",+ "name": "SDI",+ "type": "bidirectional",+ "description": "Serial I/F data input or serial I/F data input/output with internal pull-down resistor"+ },+ {+ "number": "32",+ "name": "SCLK",+ "type": "input",+ "description": "Serial I/F clock with internal pull-down resistor"+ },+ {+ "number": "33",+ "name": "TCLK–/CK1/D7",+ "type": "output",+ "description": "Negative LVDS clock output or clock output 1 or data output bit 7"+ },+ {+ "number": "34",+ "name": "TCLK+/CK0/D6",+ "type": "output",+ "description": "Positive LVDS clock output or clock output 0 or data output bit 6"+ },+ {+ "number": "35",+ "name": "TC–/D5",+ "type": "output",+ "description": "Negative TC channel LVDS data output or data output bit 5"+ },+ {+ "number": "36",+ "name": "TC+/D4",+ "type": "output",+ "description": "Positive TC channel LVDS data output or data output bit 4"+ },+ {+ "number": "37",+ "name": "TB–/D3",+ "type": "output",+ "description": "Negative TB channel LVDS data output or data output bit 3"+ },+ {+ "number": "38",+ "name": "TB+/D2",+ "type": "output",+ "description": "Positive TB channel LVDS data output or data output bit 2"+ },+ {+ "number": "39",+ "name": "TA–/D1",+ "type": "output",+ "description": "Negative TA channel LVDS data output or data output bit 1"+ },+ {+ "number": "40",+ "name": "TA+/D0",+ "type": "output",+ "description": "Positive TA channel LVDS data output or data output bit 0"+ },+ {+ "number": "41",+ "name": "LVDD",+ "type": "power_in",+ "description": "LVDS/CMOS output power supply"+ },+ {+ "number": "42",+ "name": "LVSS",+ "type": "power_in",+ "description": "LVDS/CMOS output ground"+ },+ {+ "number": "43",+ "name": "DVDD_IO",+ "type": "power_in",+ "description": "Digital I/O power supply"+ },+ {+ "number": "44",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "45",+ "name": "XLSYNC",+ "type": "bidirectional",+ "description": "Internal line synchronous signal output (default, with internal pull-down) or external line synchronous signal input"+ },+ {+ "number": "46",+ "name": "SDO/GPIO1",+ "type": "bidirectional",+ "description": "General-purpose input port 1 (default, with internal pull-down), general-purpose output port 1, or serial I/F data output"+ },+ {+ "number": "47",+ "name": "XST/GPIO3",+ "type": "bidirectional",+ "description": "General-purpose input port 3 (default, with internal pull-down), general-purpose output port 3, or XST storage pulse output"+ },+ {+ "number": "48",+ "name": "XCLR",+ "type": "output",+ "description": "Sensor clear gate output"+ },+ {+ "number": "49",+ "name": "XP1",+ "type": "output",+ "description": "Fast transfer clock output φ1"+ },+ {+ "number": "50",+ "name": "XP2",+ "type": "output",+ "description": "Fast transfer clock output φ2"+ },+ {+ "number": "51",+ "name": "XP3",+ "type": "output",+ "description": "Fast transfer clock output φ3"+ },+ {+ "number": "52",+ "name": "XP4",+ "type": "output",+ "description": "Fast transfer clock output φ4"+ },+ {+ "number": "53",+ "name": "X1L",+ "type": "output",+ "description": "Fast transfer clock output 1L"+ },+ {+ "number": "54",+ "name": "X2L",+ "type": "output",+ "description": "Fast transfer clock output 2L"+ },+ {+ "number": "55",+ "name": "XCP",+ "type": "output",+ "description": "Clamp gate clock output"+ },+ {+ "number": "56",+ "name": "XRS",+ "type": "output",+ "description": "Reset gate clock output"+ },+ {+ "number": "57",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 57 added from the footprint"+ ],+ "pages_sent": 14,+ "cost_usd": 0.2103,+ "at": "2026-10-05T20:10:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/vsp5612",+ "pages": 47,+ "sha256": "b01183c0d2c944e8",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 57,+ "described": 57,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ }+}
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vsp5610rshr-hero.glbadded⋯ 1 unchanged line ⋯
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vsp5610rshr.lbradded+279@@ -0,0 +1,279 @@+<?xml version="1.0" encoding="utf-8"?>+<!DOCTYPE eagle SYSTEM "eagle.dtd">+<eagle version="9.6.2">+<drawing>+<settings><setting alwaysvectorfont="no"/></settings>+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>+<layers>+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" 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direction="in"/>+ <pin name="AVDD_LDO" x="-17.78" y="33.02" length="middle" direction="out"/>+ <pin name="VSS" x="-17.78" y="30.48" length="middle" direction="pwr"/>+ <pin name="AIN1" x="-17.78" y="27.94" length="middle" direction="in"/>+ <pin name="AINGND1" x="-17.78" y="25.4" length="middle" direction="pwr"/>+ <pin name="AIN2" x="-17.78" y="22.86" length="middle" direction="in"/>+ <pin name="AINGND2" x="-17.78" y="20.32" length="middle" direction="pwr"/>+ <pin name="AIN3" x="-17.78" y="17.78" length="middle" direction="in"/>+ <pin name="AINGND3" x="-17.78" y="15.24" length="middle" direction="pwr"/>+ <pin name="AIN4" x="-17.78" y="12.7" length="middle" direction="in"/>+ <pin name="AINGND4" x="-17.78" y="10.16" length="middle" direction="pwr"/>+ <pin name="VSS@2" x="-17.78" y="7.62" length="middle" direction="pwr"/>+ <pin name="REF_AIN" x="-17.78" y="5.08" length="middle" direction="io"/>+ <pin name="ISET" x="-17.78" y="2.54" length="middle" direction="out"/>+ <pin name="VSS@3" x="-17.78" y="0" length="middle" direction="pwr"/>+ <pin name="REFP" x="-17.78" y="-2.54" length="middle" direction="out"/>+ <pin name="REFN" x="-17.78" y="-5.08" length="middle" direction="out"/>+ <pin name="VSS@4" x="-17.78" y="-7.62" length="middle" direction="pwr"/>+ <pin name="VDD" x="-17.78" y="-10.16" length="middle" direction="pwr"/>+ <pin name="XSH1" x="-17.78" y="-12.7" length="middle" direction="out"/>+ <pin name="XSH2" x="-17.78" y="-15.24" length="middle" direction="out"/>+ <pin name="XSH3" x="-17.78" y="-17.78" length="middle" direction="out"/>+ <pin name="XSH4" x="-17.78" y="-20.32" length="middle" direction="out"/>+ <pin name="GPIO0" x="-17.78" y="-22.86" length="middle" direction="io"/>+ <pin name="SDO/GPIO2" x="-17.78" y="-25.4" length="middle" direction="io"/>+ <pin name="DVSS" x="-17.78" y="-27.94" length="middle" direction="pwr"/>+ <pin name="RCLKN" x="-17.78" y="-30.48" length="middle" direction="in"/>+ <pin name="RCLKP" x="-17.78" y="-33.02" length="middle" direction="in"/>+ <pin name="DVSS@2" x="-17.78" y="-35.56" length="middle" direction="pwr"/>+ <pin name="EP" x="17.78" y="33.02" length="middle" direction="pas" rot="R180"/>+ <pin name="XRS" x="17.78" y="30.48" length="middle" direction="out" rot="R180"/>+ <pin name="XCP" x="17.78" y="27.94" length="middle" direction="out" rot="R180"/>+ <pin name="X2L" x="17.78" y="25.4" length="middle" direction="out" rot="R180"/>+ <pin name="X1L" x="17.78" y="22.86" length="middle" direction="out" rot="R180"/>+ <pin name="XP4" x="17.78" y="20.32" length="middle" direction="out" rot="R180"/>+ <pin name="XP3" x="17.78" y="17.78" length="middle" direction="out" rot="R180"/>+ <pin name="XP2" x="17.78" y="15.24" length="middle" direction="out" rot="R180"/>+ <pin name="XP1" x="17.78" y="12.7" length="middle" direction="out" rot="R180"/>+ <pin name="XCLR" x="17.78" y="10.16" length="middle" direction="out" rot="R180"/>+ <pin name="XST/GPIO3" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="SDO/GPIO1" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="XLSYNC" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="DVSS@3" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>+ <pin name="DVDD_IO" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="LVSS" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+ <pin name="LVDD" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="TA+/D0" x="17.78" y="-10.16" length="middle" direction="out" rot="R180"/>+ <pin name="TA_/D1" x="17.78" y="-12.7" length="middle" direction="out" rot="R180"/>+ <pin name="TB+/D2" x="17.78" y="-15.24" length="middle" direction="out" rot="R180"/>+ <pin name="TB_/D3" x="17.78" y="-17.78" length="middle" direction="out" rot="R180"/>+ <pin name="TC+/D4" x="17.78" y="-20.32" length="middle" direction="out" rot="R180"/>+ <pin name="TC_/D5" x="17.78" y="-22.86" length="middle" direction="out" rot="R180"/>+ <pin name="TCLK+/CK0/D6" x="17.78" y="-25.4" length="middle" direction="out" rot="R180"/>+ <pin name="TCLK_/CK1/D7" x="17.78" y="-27.94" length="middle" direction="out" rot="R180"/>+ <pin name="SCLK" x="17.78" y="-30.48" length="middle" direction="in" rot="R180"/>+ <pin name="SDI" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="SEN" x="17.78" y="-35.56" length="middle" direction="in" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="VSP5610RSHR" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="VSP5610RSHR" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm">+ <connects>+ <connect gate="G$1" pin="TEST" pad="1"/>+ <connect gate="G$1" pin="AVDD_LDO" pad="2"/>+ <connect gate="G$1" pin="VSS" pad="3"/>+ <connect gate="G$1" pin="AIN1" pad="4"/>+ <connect gate="G$1" pin="AINGND1" pad="5"/>+ <connect gate="G$1" pin="AIN2" pad="6"/>+ <connect gate="G$1" pin="AINGND2" pad="7"/>+ <connect gate="G$1" pin="AIN3" pad="8"/>+ <connect gate="G$1" pin="AINGND3" pad="9"/>+ <connect gate="G$1" pin="AIN4" pad="10"/>+ <connect gate="G$1" pin="AINGND4" pad="11"/>+ <connect gate="G$1" pin="VSS@2" pad="12"/>+ <connect gate="G$1" pin="REF_AIN" pad="13"/>+ <connect gate="G$1" pin="ISET" pad="14"/>+ <connect gate="G$1" pin="VSS@3" pad="15"/>+ <connect gate="G$1" pin="REFP" pad="16"/>+ <connect gate="G$1" pin="REFN" pad="17"/>+ <connect gate="G$1" pin="VSS@4" pad="18"/>+ <connect gate="G$1" pin="VDD" pad="19"/>+ <connect gate="G$1" pin="XSH1" pad="20"/>+ <connect gate="G$1" pin="XSH2" pad="21"/>+ <connect gate="G$1" pin="XSH3" pad="22"/>+ <connect gate="G$1" pin="XSH4" pad="23"/>+ <connect gate="G$1" pin="GPIO0" pad="24"/>+ <connect gate="G$1" pin="SDO/GPIO2" pad="25"/>+ <connect gate="G$1" pin="DVSS" pad="26"/>+ <connect gate="G$1" pin="RCLKN" pad="27"/>+ <connect gate="G$1" pin="RCLKP" pad="28"/>+ <connect gate="G$1" pin="DVSS@2" pad="29"/>+ <connect gate="G$1" pin="EP" pad="57"/>+ <connect gate="G$1" pin="XRS" pad="56"/>+ <connect gate="G$1" pin="XCP" pad="55"/>+ <connect gate="G$1" pin="X2L" pad="54"/>+ <connect gate="G$1" pin="X1L" pad="53"/>+ <connect gate="G$1" pin="XP4" pad="52"/>+ <connect gate="G$1" pin="XP3" pad="51"/>+ <connect gate="G$1" pin="XP2" pad="50"/>+ <connect gate="G$1" pin="XP1" pad="49"/>+ <connect gate="G$1" pin="XCLR" pad="48"/>+ <connect gate="G$1" pin="XST/GPIO3" pad="47"/>+ <connect gate="G$1" pin="SDO/GPIO1" pad="46"/>+ <connect gate="G$1" pin="XLSYNC" pad="45"/>+ <connect gate="G$1" pin="DVSS@3" pad="44"/>+ <connect gate="G$1" pin="DVDD_IO" pad="43"/>+ <connect gate="G$1" pin="LVSS" pad="42"/>+ <connect gate="G$1" pin="LVDD" pad="41"/>+ <connect gate="G$1" pin="TA+/D0" pad="40"/>+ <connect gate="G$1" pin="TA_/D1" pad="39"/>+ <connect gate="G$1" pin="TB+/D2" pad="38"/>+ <connect gate="G$1" pin="TB_/D3" pad="37"/>+ <connect gate="G$1" pin="TC+/D4" pad="36"/>+ <connect gate="G$1" pin="TC_/D5" pad="35"/>+ <connect gate="G$1" pin="TCLK+/CK0/D6" pad="34"/>+ <connect gate="G$1" pin="TCLK_/CK1/D7" pad="33"/>+ <connect gate="G$1" pin="SCLK" pad="32"/>+ <connect gate="G$1" pin="SDI" pad="31"/>+ <connect gate="G$1" pin="SEN" pad="30"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
vsp5610rshr.stepadded+17392@@ -0,0 +1,17392 @@+ISO-10303-21;+HEADER;+/* QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2022, KiCAD+ * + * This work is licensed under the+ * [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),+ * with the following exception:+ * + * To the extent that the creation of electronic designs that use 'Licensed Material' can be+ * considered to be 'Adapted Material', then the copyright holder waives article 3 of the license+ * with respect to these designs and any generated files which use data provided as part of the+ * 'Licensed Material'.+ * + * You are free to use the library data in your own projects without the obligation to share your+ * project files under this or any other license agreement. However, if you wish to distribute+ * these libraries, or parts thereof (including in modified form) as a collection then the exception+ * above does not apply. Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ * + * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm.step',+/* time_stamp */ '2022-12-29T13:23:49',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1 = APPLICATION_PROTOCOL_DEFINITION('international standard',+'automotive_design',2000,#2);+#2 = APPLICATION_CONTEXT(+'core data for automotive mechanical design processes');+#3 = SHAPE_DEFINITION_REPRESENTATION(#4,#10);+#4 = PRODUCT_DEFINITION_SHAPE('','',#5);+#5 = PRODUCT_DEFINITION('design','',#6,#9);+#6 = PRODUCT_DEFINITION_FORMATION('','',#7);+#7 = PRODUCT('CQ assembly','CQ assembly','',(#8));+#8 = PRODUCT_CONTEXT('',#2,'mechanical');+#9 = PRODUCT_DEFINITION_CONTEXT('part definition',#2,'design');+#10 = SHAPE_REPRESENTATION('',(#11,#15),#19);+#11 = AXIS2_PLACEMENT_3D('',#12,#13,#14);+#12 = CARTESIAN_POINT('',(0.,0.,0.));+#13 = DIRECTION('',(0.,0.,1.));+#14 = DIRECTION('',(1.,0.,-0.));+#15 = AXIS2_PLACEMENT_3D('',#16,#17,#18);+#16 = CARTESIAN_POINT('',(0.,0.,0.));+#17 = DIRECTION('',(0.,0.,1.));+#18 = DIRECTION('',(1.,0.,-0.));+#19 = ( GEOMETRIC_REPRESENTATION_CONTEXT(3)+GLOBAL_UNCERTAINTY_ASSIGNED_CONTEXT((#23)) GLOBAL_UNIT_ASSIGNED_CONTEXT(+(#20,#21,#22)) REPRESENTATION_CONTEXT('Context #1',+'3D Context with UNIT and UNCERTAINTY') );+#20 = ( LENGTH_UNIT() NAMED_UNIT(*) SI_UNIT(.MILLI.,.METRE.) );+#21 = ( NAMED_UNIT(*) PLANE_ANGLE_UNIT() SI_UNIT($,.RADIAN.) );+#22 = ( NAMED_UNIT(*) SI_UNIT($,.STERADIAN.) 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