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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

VSP5324TRGCRQ1

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)

VSP5324TRGCRQ1 from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN1_P	input	Channel 1 positive differential analog input.
2	IN1_M	input	Channel 1 negative differential analog input.
3	AGND	power_in	Analog ground pin.
4	NC	unconnected	Unused; do not connect.
5	NC	unconnected	Unused; do not connect.
6	AGND	power_in	Analog ground pin.
7	IN2_P	input	Channel 2 positive differential analog input.
8	IN2_M	input	Channel 2 negative differential analog input.
9	AGND	power_in	Analog ground pin.
10	NC	unconnected	Unused; do not connect.
11	NC	unconnected	Unused; do not connect.
12	LGND	power_in	Digital ground pin.
13	PD	input	Power-down control input pin; logic high puts the device in power-down state and logic low gives normal operation.
14	LGND	power_in	Digital ground pin.
15	OUT1A_P	output	Channel 1A positive LVDS differential output pin, usable with one- or two-lane interface.
16	OUT1A_M	output	Channel 1A negative LVDS differential output pin, usable with one- or two-lane interface.
17	OUT1B_P	output	Channel 1B positive LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
18	OUT1B_M	output	Channel 1B negative LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
19	OUT2A_P	output	Channel 2A positive LVDS differential output pin, usable with one- or two-lane interface.
20	OUT2A_M	output	Channel 2A negative LVDS differential output pin, usable with one- or two-lane interface.
21	OUT2B_P	output	Channel 2B positive LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
22	OUT2B_M	output	Channel 2B negative LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
23	ADCLKP	output	Positive LVDS differential frame clock output pin.
24	ADCLKM	output	Negative LVDS differential frame clock output pin.
25	LCLKP	output	Positive LVDS differential bit clock output pin.
26	LCLKM	output	Negative LVDS differential bit clock output pin.
27	OUT3B_P	output	Channel 3B positive LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
28	OUT3B_M	output	Channel 3B negative LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
29	OUT3A_P	output	Channel 3A positive LVDS differential output pin, usable with one- or two-lane interface.
30	OUT3A_M	output	Channel 3A negative LVDS differential output pin, usable with one- or two-lane interface.
31	OUT4B_P	output	Channel 4B positive LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
32	OUT4B_M	output	Channel 4B negative LVDS differential output pin used with two-lane interface; in one-lane interface it is unused and must be floated without a 100-Ω termination.
33	OUT4A_P	output	Channel 4A positive LVDS differential output pin, usable with one- or two-lane interface.
34	OUT4A_M	output	Channel 4A negative LVDS differential output pin, usable with one- or two-lane interface.
35	LVDD	power_in	Digital and LVDS supply pin, 1.8 V nominal.
36	LGND	power_in	Digital ground pin.
37	AGND	power_in	Analog ground pin.
38	NC	unconnected	Unused; do not connect.
39	NC	unconnected	Unused; do not connect.
40	AGND	power_in	Analog ground pin.
41	IN3_P	input	Channel 3 positive differential analog input.
42	IN3_M	input	Channel 3 negative differential analog input.
43	AGND	power_in	Analog ground pin.
44	NC	unconnected	Unused; do not connect.
45	NC	unconnected	Unused; do not connect.
46	AGND	power_in	Analog ground pin.
47	IN4_P	input	Channel 4 positive differential analog input.
48	IN4_M	input	Channel 4 negative differential analog input.
49	SYNC	input	Control input pin that synchronizes test patterns across channels; tie to ground when unused.
50	AVDD	power_in	Analog supply pin, 1.8 V nominal.
51	NC	unconnected	Unused; do not connect.
52	SDOUT	output	Serial interface readout pin; high-impedance by default and driven only when serial readout mode is enabled.
53	VCM	output	Common-mode voltage pin: 0.95 V output in internal reference mode; in external reference mode the reference voltage must be applied externally (1.5 V ±50 mV per the external reference section).
54	REFB	input	Reference bottom voltage pin: outputs 0.45 V in internal reference mode and must be externally applied at 0.45 V in external reference mode.
55	REFT	input	Reference top voltage pin: outputs 1.45 V in internal reference mode and must be externally applied at 1.45 V in external reference mode.
56	INT/EXT	input	Internal/external reference control input: logic high selects the internal reference and logic low selects the external reference.
57	AVDD	power_in	Analog supply pin, 1.8 V nominal.
58	CLKP	input	Positive clock input; differential clocks (sine wave, LVPECL, LVDS) go to CLKP/CLKM, or a CMOS clock goes to CLKP with CLKM tied to ground for single-ended operation.
59	CLKM	input	Negative clock input; differential clocks go to CLKP/CLKM, or CLKM is tied to ground for single-ended CMOS clock operation.
60	AVDD	power_in	Analog supply pin, 1.8 V nominal.
61	CS	input	Serial interface enable pin; serial data is shifted in while CS is low.
62	SDATA	input	Serial interface data pin; data is latched on each SCLK rising edge.
63	SCLK	input	Serial interface clock pin; SCLK frequencies up to 15 MHz are supported.
64	RESET	input	Serial interface reset pin, active low; a low pulse wider than 10 ns performs a hardware reset.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	ADC/DAC/Data Conversion
Pins	65

CAD (KiCad official)

Symbol: VSP5324TRGCRQ1
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: vsp5324trgcrq1-etched.step / vsp5324trgcrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsp5324trgcrq1.step / vsp5324trgcrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (65 pp, sha256 753225536917052d, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF