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VSP2582RHN

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Texas Instruments Analog Front End (AFE), VQFN-36(6.2x6.2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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VSP2582RHN

Texas Instruments · Analog Front End (AFE) · VQFN-36(6.2x6.2)

VSP2582RHN from Texas Instruments, in a VQFN-36(6.2x6.2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B2 output Data output bit 2 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
2 B3 output Data output bit 3 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
3 B4 output Data output bit 4 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
4 B5 output Data output bit 5 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
5 B6 output Data output bit 6 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
6 B7 output Data output bit 7 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
7 B8 output Data output bit 8 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
8 B9 output Data output bit 9 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
9 B10 output Data output bit 10 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
10 B11 output Data output bit 11, the MSB, of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
11 VDD power_in Digital power supply for the data output, specified at 2.7 V to 3.6 V (3.0 V nominal); VDD should be decoupled close to DGND.
12 DGND power_in Digital ground for the data output.
13 ADCCK input Clock input for the digital output buffer, with ADCCK high or low level timing given in the timing specifications.
14 VCC power_in Analog power supply, specified at 2.7 V to 3.6 V (3.0 V nominal).
15 CLPDM input CLPDM timing signal input; CMOS logic input with VT+ of 1.7 V and VT- of 1.0 V, and the datasheet gives no further function description.
16 CLPOB input CLPOB timing signal input; CMOS logic input with VT+ of 1.7 V and VT- of 1.0 V, and the datasheet gives no further function description.
17 SHP input Sampling clock for the reference level of the CCD signal, with SHP pulse width of 5.9 ns min to 6.9 ns at 36 MHz operation.
18 SHD input Sampling clock for the data level of the CCD signal, with SHD pulse width of 5.9 ns min to 6.9 ns at 36 MHz operation.
19 AGND power_in Analog ground.
20 VCC power_in Analog power supply, specified at 2.7 V to 3.6 V (3.0 V nominal).
21 VCC power_in Analog power supply, specified at 2.7 V to 3.6 V (3.0 V nominal).
22 AGND power_in Analog ground.
23 AGND power_in Analog ground.
24 CCDIN input CCD signal input, with an input limit of -0.3 V to 3.3 V and input capacitance of 15 pF.
25 BYP output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
26 BYPP output Internal reference bypass pin, to be bypassed to ground with 1000 pF; the datasheet notes this capacitor sets important analog performance.
27 COB output Optical black loop feedback capacitor pin, with recommended value 0.1 μF.
28 REFN output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
29 REFP output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
30 VCC power_in Analog power supply, specified at 2.7 V to 3.6 V (3.0 V nominal).
31 AGND power_in Analog ground.
32 SLOAD input Serial data latch signal input, CMOS logic family.
33 SDATA input Serial data input, CMOS logic family.
34 SCLK input Serial data clock input, with a maximum digital input clock frequency of 20 MHz.
35 B0 output Data output bit 0, the LSB, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
36 B1 output Data output bit 1 of the 12-bit ADC output, CMOS logic with VOH of 2.4 V min and VOL of 0.4 V max.
37 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-36(6.2x6.2)
Category Data Acquisition
Pins 37

CAD (KiCad official)

  • Symbol: VSP2582RHN
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: VQFN-36(6.2x6.2) (KiCad packages3D, STEP)
  • 3D model files: vsp2582rhn-etched.step / vsp2582rhn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsp2582rhn.step / vsp2582rhn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 b1e5ff8f24ae00bc, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF