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VSP2582RHHR

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Texas Instruments Analog Front End (AFE), VQFN-36(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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VSP2582RHHR

Texas Instruments · Analog Front End (AFE) · VQFN-36(6x6)

VSP2582RHHR from Texas Instruments, in a VQFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B2 output Digital data output bit 2 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
2 B3 output Digital data output bit 3 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
3 B4 output Digital data output bit 4 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
4 B5 output Digital data output bit 5 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
5 B6 output Digital data output bit 6 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
6 B7 output Digital data output bit 7 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
7 B8 output Digital data output bit 8 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
8 B9 output Digital data output bit 9 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
9 B10 output Digital data output bit 10 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
10 B11 output Digital data output bit 11, the MSB (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
11 VDD power_in Digital power supply for data output, 2.7 V to 3.6 V (3.0 V nominal); decouple close to DGND.
12 DGND power_in Digital ground for data output; VDD should be decoupled to the proximity of DGND.
13 ADCCK input Clock for the digital output buffer; ADCCK high or low level is specified as 6.5 to 21.2 ns at 36 MHz operation.
14 VCC power_in Analog power supply, 2.7 V to 3.6 V (3.0 V nominal).
15 CLPDM input CLPDM clamp signal input for the CCD black level clamping function.
16 CLPOB input CLPOB clamp signal input for the optical black clamp function.
17 SHP input Sampling clock for the reference level of the CCD signal; SHP pulse width is 5.9 to 6.9 ns at 36 MHz operation.
18 SHD input Sampling clock for the data level of the CCD signal; SHD pulse width is 5.9 to 6.9 ns at 36 MHz operation.
19 AGND power_in Analog ground.
20 VCC power_in Analog power supply, 2.7 V to 3.6 V (3.0 V nominal).
21 VCC power_in Analog power supply, 2.7 V to 3.6 V (3.0 V nominal).
22 AGND power_in Analog ground.
23 AGND power_in Analog ground.
24 CCDIN input CCD signal input; the datasheet gives an input limit of -0.3 V to 3.3 V and an input capacitance of 15 pF.
25 BYP output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
26 BYPP output Internal reference bypass pin, to be bypassed to ground with 1000 pF; the datasheet notes this capacitor sets important analog performance and should be placed close to the pin.
27 COB output OB loop feedback capacitor pin; the recommended value is 0.1 μF and it sets important analog performance.
28 REFN output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
29 REFP output Internal reference bypass pin, to be bypassed to ground with 0.1 μF.
30 VCC power_in Analog power supply, 2.7 V to 3.6 V (3.0 V nominal).
31 AGND power_in Analog ground.
32 SLOAD input Serial data latch signal for the serial interface; CMOS logic input.
33 SDATA input Serial data input for the serial interface; CMOS logic input.
34 SCLK input Serial data clock for the serial interface; maximum digital input clock frequency is 20 MHz.
35 B0 output Digital data output bit 0, the LSB (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
36 B1 output Digital data output bit 1 (CMOS, straight binary coding); datasheet lists VOH 2.4 V and VOL 0.4 V for the data outputs.
37 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-36(6x6)
Category Data Acquisition
Pins 37

CAD (KiCad official)

  • Symbol: VSP2582RHHR
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: VQFN-36(6x6) (KiCad packages3D, STEP)
  • 3D model files: vsp2582rhhr-etched.step / vsp2582rhhr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsp2582rhhr.step / vsp2582rhhr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 b1e5ff8f24ae00bc, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF