# VSP004N10MS-K

**Vergiga(威兆)** · MOSFETs · DFN-8(5.1x6.1)

VSP004N10MS-K from Vergiga(威兆), in a DFN-8(5.1x6.1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source pin; pins 1-3 are the source of the N-channel MOSFET (VDS 100 V, ID 90 A silicon limited / 50 A package limited). |
| 2 | S | passive | Source pin; pins 1-3 are the source of the N-channel MOSFET (VDS 100 V, ID 90 A silicon limited / 50 A package limited). |
| 3 | S | passive | Source pin; pins 1-3 are the source of the N-channel MOSFET (VDS 100 V, ID 90 A silicon limited / 50 A package limited). |
| 4 | G | input | Gate pin; gate-source voltage rated at ±20 V with threshold 1.4 to 2.3 V. |
| 5 | D | passive | Drain pin; pins 5-8 are the drain, connected to the exposed drain tab, with VDS rated at 100 V. |
| 6 | D | passive | Drain pin; pins 5-8 are the drain, connected to the exposed drain tab, with VDS rated at 100 V. |
| 7 | D | passive | Drain pin; pins 5-8 are the drain, connected to the exposed drain tab, with VDS rated at 100 V. |
| 8 | D | passive | Drain pin; pins 5-8 are the drain, connected to the exposed drain tab, with VDS rated at 100 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vergiga(威兆) |
| Package | DFN-8(5.1x6.1) |
| Category | Transistors/Thyristors |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | 100 |  |  | V | VGS=0V, ID=250μA | 2 |
| Zero Gate Voltage Drain Current (Tj=25°C) | IDSS |  |  | 1 | μA | VDS=100V, VGS=0V | 2 |
| Zero Gate Voltage Drain Current (Tj=125°C) | IDSS |  |  | 100 | μA | VDS=100V, VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V | 2 |
| Gate Threshold Voltage | VGS(th) | 1.4 | 1.8 | 2.3 | V | VDS=VGS, ID=250μA | 2 |
| Drain-Source On-State Resistance | RDS(on) |  | 5 | 6.5 | mΩ | VGS=10V, ID=40A | 2 |
| Drain-Source On-State Resistance | RDS(on) |  | 6.9 | 9 | mΩ | VGS=4.5V, ID=20A | 2 |
| Input Capacitance | Ciss | 2325 | 3100 | 4125 | pF | VDS=30V, VGS=0V, f=1MHz | 2 |
| Output Capacitance | Coss | 1060 | 1415 | 1880 | pF |  | 2 |
| Reverse Transfer Capacitance | Crss | 20 | 35 | 50 | pF |  | 2 |
| Gate Resistance | Rg | 0.2 | 0.5 | 3 | Ω | f=1MHz | 2 |
| Total Gate Charge (10V) | Qg(10V) |  | 49 | 65 | nC |  | 2 |
| Total Gate Charge (4.5V) | Qg(4.5V) |  | 25 | 33 | nC |  | 2 |
| Gate-Source Charge | Qgs |  | 9.8 | 13 | nC |  | 2 |
| Gate-Drain Charge | Qgd |  | 9.5 | 14 | nC |  | 2 |
| Forward on voltage | VSD |  | 0.9 | 1.2 | V | ISD=40A, VGS=0V | 2 |
| Reverse Recovery Time | Trr |  | 48 | 96 | ns | Isd=40A, VGS=0V, di/dt=100A/μs | 2 |
| Reverse Recovery Charge | Qrr |  | 44 | 88 | nC |  | 2 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Diode continuous forward current | IS |  |  | 90 | A | TC = 25°C | 1 |
| Continuous drain current (Silicon limited) | ID |  |  | 90 | A | @VGS=10V, TC = 25°C | 1 |
| Continuous drain current (Silicon limited) | ID |  |  | 57 | A | @VGS=10V, TC = 100°C | 1 |
| Continuous drain current (Package limited) | ID |  |  | 50 | A | @VGS=10V, TC = 25°C | 1 |
| Pulse drain current tested | IDM |  |  | 360 | A | TC = 25°C | 1 |
| Continuous drain current | IDSM |  |  | 22 | A | @VGS=10V, TA = 25°C | 1 |
| Continuous drain current | IDSM |  |  | 17 | A | @VGS=10V, TA = 70°C | 1 |
| Avalanche energy, single pulsed | EAS |  |  | 36 | mJ |  | 1 |
| Maximum power dissipation | PD |  |  | 74 | W | TC = 25°C | 1 |
| Maximum power dissipation | PD |  |  | 29 | W | TC = 100°C | 1 |
| Maximum power dissipation | PDSM |  |  | 4.2 | W | TA = 25°C | 1 |
| Maximum power dissipation | PDSM |  |  | 2.7 | W | TA = 70°C | 1 |
| Storage and Junction Temperature Range | TSTG,TJ | -55 |  | 150 | °C |  | 1 |
| Thermal Resistance, Junction-to-Case | RθJC |  | 1.7 | 2 | °C/W |  | 1 |
| Thermal Resistance, Junction-to-Ambient | RθJA |  | 30 | 36 | °C/W |  | 1 |

## CAD (KiCad official)

- Symbol: `VSP004N10MS-K`
- Footprint: `Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm`
- 3D model: DFN-8(5.1x6.1) (KiCad packages3D, STEP)
- 3D model files: `vsp004n10ms-k-etched.step` / `vsp004n10ms-k-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vsp004n10ms-k.step` / `vsp004n10ms-k.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vergiga(威兆) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906243349360640) (7 pp, sha256 `30b3814cace49de2`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/vsp004n10ms-k-datasheet.pdf)