VSC8664XIC from Microchip Tech, in a BGA-256(17x17). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
A1	NC	unconnected	No-connect ball; leave floating and do not connect it to other pins or ground.
A2	TXVPA_3	passive	Channel A positive TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
A3	TXVPB_3	passive	Channel B positive TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
A4	TXVPC_3	passive	Channel C positive TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
A5	TXVPD_3	passive	Channel D positive TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
A6	TXVPA_2	passive	Channel A positive TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
A7	TXVPB_2	passive	Channel B positive TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
A8	TXVPC_2	passive	Channel C positive TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
A9	TXVPD_2	passive	Channel D positive TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
A10	TXVPA_1	passive	Channel A positive TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
A11	TXVPB_1	passive	Channel B positive TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
A12	TXVPC_1	passive	Channel C positive TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
A13	TXVPD_1	passive	Channel D positive TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
A14	TXVPA_0	passive	Channel A positive TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
A15	TXVPB_0	passive	Channel B positive TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
A16	NC	unconnected	No-connect ball; leave floating and do not connect it to other pins or ground.
B1	VSS	power_in	0 V general device ground.
B2	TXVNA_3	passive	Channel A negative TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
B3	TXVNB_3	passive	Channel B negative TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
B4	TXVNC_3	passive	Channel C negative TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
B5	TXVND_3	passive	Channel D negative TX/RX signal of the twisted pair interface on PHY 3 (ADIFF).
B6	TXVNA_2	passive	Channel A negative TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
B7	TXVNB_2	passive	Channel B negative TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
B8	TXVNC_2	passive	Channel C negative TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
B9	TXVND_2	passive	Channel D negative TX/RX signal of the twisted pair interface on PHY 2 (ADIFF).
B10	TXVNA_1	passive	Channel A negative TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
B11	TXVNB_1	passive	Channel B negative TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
B12	TXVNC_1	passive	Channel C negative TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
B13	TXVND_1	passive	Channel D negative TX/RX signal of the twisted pair interface on PHY 1 (ADIFF).
B14	TXVNA_0	passive	Channel A negative TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
B15	TXVNB_0	passive	Channel B negative TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
B16	VSS	power_in	0 V general device ground.
C1	XTAL2	passive	Crystal oscillator output; connect the crystal across XTAL1 and XTAL2 with 33 pF to ground, or leave floating when driving XTAL1/REFCLK with a reference clock.
C2	VDD33	power_in	General 3.3 V power supply.
C3	VSS	power_in	0 V general device ground.
C4	VDD33	power_in	General 3.3 V power supply.
C5	VSS	power_in	0 V general device ground.
C6	VDD33	power_in	General 3.3 V power supply.
C7	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
C8	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
C9	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
C10	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
C11	VDD33	power_in	General 3.3 V power supply.
C12	VSS	power_in	0 V general device ground.
C13	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
C14	VDD33	power_in	General 3.3 V power supply.
C15	TXVNC_0	passive	Channel C negative TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
C16	TXVPC_0	passive	Channel C positive TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
D1	XTAL1/REFCLK	input	Crystal input when OSCEN is high (25 MHz parallel-resonant crystal, ±50 ppm, with 33 pF to ground); reference clock input when OSCEN is low (25 MHz with PLLMODE low, or 125 MHz with PLLMODE high).
D2	OSCEN	input	Oscillator enable, sampled on the rising edge of NRESET; high enables the on-chip oscillator, and low or floating disables it.
D3	REF_FILT	passive	Reference filter pin; connect to an external 1 µF capacitor to analog ground.
D4	REF_REXT	passive	Reference external pin; connect to an external 2 kΩ (1%) resistor to analog ground.
D5	VSS	power_in	0 V general device ground.
D6	VSS	power_in	0 V general device ground.
D7	VSS	power_in	0 V general device ground.
D8	VSS	power_in	0 V general device ground.
D9	VSS	power_in	0 V general device ground.
D10	VSS	power_in	0 V general device ground.
D11	VSS	power_in	0 V general device ground.
D12	VSS	power_in	0 V general device ground.
D13	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
D14	CMODE5	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
D15	TXVND_0	passive	Channel D negative TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
D16	TXVPD_0	passive	Channel D positive TX/RX signal of the twisted pair interface on PHY 0 (ADIFF).
E1	PLLMODE	input	PLL mode select sampled at power-up or reset; low requires a 25 MHz REFCLK, high requires 125 MHz, and it must be pulled low when using a crystal.
E2	TMS	input	JTAG test mode select input, with on-chip pull-up to VDD33; 5 V tolerant.
E3	NTRST	input	JTAG reset input, with on-chip pull-up to VDD33; when JTAG is not used, tie it to VSS with a pull-down resistor.
E4	VDD33	power_in	General 3.3 V power supply.
E5	VDD12	power_in	1.2 V supply for the internal digital logic.
E6	VSS	power_in	0 V general device ground.
E7	VSS	power_in	0 V general device ground.
E8	VSS	power_in	0 V general device ground.
E9	VSS	power_in	0 V general device ground.
E10	VSS	power_in	0 V general device ground.
E11	VSS	power_in	0 V general device ground.
E12	VDD12	power_in	1.2 V supply for the internal digital logic.
E13	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
E14	CMODE4	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
E15	CMODE6	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
E16	CMODE7	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
F1	TDO	output	JTAG test serial data output, with on-chip pull-up to VDDIO.
F2	TDI	input	JTAG test serial data input, with on-chip pull-up to VDD33; 5 V tolerant.
F3	TCK	input	JTAG test clock input, with on-chip pull-up to VDD33; 5 V tolerant.
F4	VSS	power_in	0 V general device ground.
F5	VDD12	power_in	1.2 V supply for the internal digital logic.
F6	VSS	power_in	0 V general device ground.
F7	VSS	power_in	0 V general device ground.
F8	VSS	power_in	0 V general device ground.
F9	VSS	power_in	0 V general device ground.
F10	VSS	power_in	0 V general device ground.
F11	VSS	power_in	0 V general device ground.
F12	VDD12	power_in	1.2 V supply for the internal digital logic.
F13	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
F14	CMODE2	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
F15	CMODE3	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
F16	RCVRD_CLK1	output	Recovered clock output 1, enabled through register 23G and selectable at 125 MHz or 25 MHz; held low when disabled or when NRESET or NSRESET is asserted.
G1	LED0_0	output	Active-low LED direct-drive output for PHY 0 LED 0, driven from VDD33 at 3.3 V; can carry the serial LED stream.
G2	LED1_0	output	Active-low LED direct-drive output for PHY 0 LED 1, driven from VDD33 at 3.3 V; can carry the serial LED clock.
G3	LED2_0	output	Active-low LED direct-drive output for PHY 0 LED 2, driven from VDD33 at 3.3 V.
G4	LED3_0	output	Active-low LED direct-drive output for PHY 0 LED 3, driven from VDD33 at 3.3 V.
G5	VDD12	power_in	1.2 V supply for the internal digital logic.
G6	VSS	power_in	0 V general device ground.
G7	VSS	power_in	0 V general device ground.
G8	VSS	power_in	0 V general device ground.
G9	VSS	power_in	0 V general device ground.
G10	VSS	power_in	0 V general device ground.
G11	VSS	power_in	0 V general device ground.
G12	VDD12	power_in	1.2 V supply for the internal digital logic.
G13	CMODE0	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
G14	CMODE1	passive	Configuration mode (CMODE) analog input used to set device functions at reset.
G15	CLKOUT	output	Clock output of 125 MHz that can be enabled or disabled; held low when disabled and not active while NRESET is asserted.
G16	RCVRD_CLK2	output	Recovered clock output 2, enabled through register 24G and selectable at 125 MHz or 25 MHz; held low when disabled or when NRESET or NSRESET is asserted.
H1	LED0_1	output	Active-low LED direct-drive output for PHY 1 LED 0, driven from VDD33 at 3.3 V.
H2	LED1_1	output	Active-low LED direct-drive output for PHY 1 LED 1, driven from VDD33 at 3.3 V.
H3	LED2_1	output	Active-low LED direct-drive output for PHY 1 LED 2, driven from VDD33 at 3.3 V.
H4	LED3_1	output	Active-low LED direct-drive output for PHY 1 LED 3, driven from VDD33 at 3.3 V.
H5	VDD12	power_in	1.2 V supply for the internal digital logic.
H6	VSS	power_in	0 V general device ground.
H7	VSS	power_in	0 V general device ground.
H8	VSS	power_in	0 V general device ground.
H9	VSS	power_in	0 V general device ground.
H10	VSS	power_in	0 V general device ground.
H11	VSS	power_in	0 V general device ground.
H12	VDD12	power_in	1.2 V supply for the internal digital logic.
H13	VDD33	power_in	General 3.3 V power supply.
H14	GPIO13	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
H15	THERMDC	passive	Thermal diode cathode (n-junction), connected internally to VSS.
H16	THERMDA	passive	Thermal diode anode (p-junction).
J1	LED0_2	output	Active-low LED direct-drive output for PHY 2 LED 0, driven from VDD33 at 3.3 V.
J2	LED1_2	output	Active-low LED direct-drive output for PHY 2 LED 1, driven from VDD33 at 3.3 V.
J3	LED2_2	output	Active-low LED direct-drive output for PHY 2 LED 2, driven from VDD33 at 3.3 V.
J4	LED3_2	output	Active-low LED direct-drive output for PHY 2 LED 3, driven from VDD33 at 3.3 V.
J5	VDD12	power_in	1.2 V supply for the internal digital logic.
J6	VSS	power_in	0 V general device ground.
J7	VSS	power_in	0 V general device ground.
J8	VSS	power_in	0 V general device ground.
J9	VSS	power_in	0 V general device ground.
J10	VSS	power_in	0 V general device ground.
J11	VSS	power_in	0 V general device ground.
J12	VDD12	power_in	1.2 V supply for the internal digital logic.
J13	VSS	power_in	0 V general device ground.
J14	GPIO12	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
J15	GPIO14	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
J16	GPIO15	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
K1	LED0_3	output	Active-low LED direct-drive output for PHY 3 LED 0, driven from VDD33 at 3.3 V.
K2	LED1_3	output	Active-low LED direct-drive output for PHY 3 LED 1, driven from VDD33 at 3.3 V.
K3	LED2_3	output	Active-low LED direct-drive output for PHY 3 LED 2, driven from VDD33 at 3.3 V.
K4	LED3_3	output	Active-low LED direct-drive output for PHY 3 LED 3, driven from VDD33 at 3.3 V.
K5	VDD12	power_in	1.2 V supply for the internal digital logic.
K6	VSS	power_in	0 V general device ground.
K7	VSS	power_in	0 V general device ground.
K8	VSS	power_in	0 V general device ground.
K9	VSS	power_in	0 V general device ground.
K10	VSS	power_in	0 V general device ground.
K11	VSS	power_in	0 V general device ground.
K12	VDD12	power_in	1.2 V supply for the internal digital logic.
K13	GPIO8/I2C_SDA	bidirectional	General-purpose input/output that can also serve as the I2C controller SDA pin if not used as GPIO.
K14	GPIO9/FastLinkFail	bidirectional	General-purpose input/output that also serves as the fast link failure indicator, asserting high when a link fails and the feature is enabled.
K15	GPIO10	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
K16	GPIO11	bidirectional	General-purpose input/output with on-chip pull-up to VDDIO or VDD33; can be used as a GPIO pin.
L1	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
L2	MDINT3	output	Management interrupt output for PHY 3, configured as active-low open-drain or active-high open-source by an external resistor at reset.
L3	NSRESET	input	Active-low device soft reset input; powers down the device, while register bits marked sticky keep their values.
L4	VSS	power_in	0 V general device ground.
L5	VDD12	power_in	1.2 V supply for the internal digital logic.
L6	VSS	power_in	0 V general device ground.
L7	VSS	power_in	0 V general device ground.
L8	VSS	power_in	0 V general device ground.
L9	VSS	power_in	0 V general device ground.
L10	VSS	power_in	0 V general device ground.
L11	VSS	power_in	0 V general device ground.
L12	VDD12	power_in	1.2 V supply for the internal digital logic.
L13	GPIO4/I2C_SCL_0	bidirectional	General-purpose input/output that can also serve as the I2C controller SCL pin for mux port 0 if not used as GPIO.
L14	GPIO5/I2C_SCL_1	bidirectional	General-purpose input/output that can also serve as the I2C controller SCL pin for mux port 1 if not used as GPIO.
L15	GPIO6/I2C_SCL_2	bidirectional	General-purpose input/output that can also serve as the I2C controller SCL pin for mux port 2 if not used as GPIO.
L16	GPIO7/I2C_SCL_3	bidirectional	General-purpose input/output that can also serve as the I2C controller SCL pin for mux port 3 if not used as GPIO.
M1	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
M2	MDINT0	output	Management interrupt output for PHY 0, configured as active-low open-drain or active-high open-source by an external resistor at reset.
M3	NRESET	input	Active-low device reset input; powers down the device and sets all register bits to their default state.
M4	VDDIO	power_in	I/O power supply for MDC, MDIO, MDINTn and NRESET, selectable at 3.3 V, 2.5 V or 1.8 V.
M5	VDD12	power_in	1.2 V supply for the internal digital logic.
M6	VSS	power_in	0 V general device ground.
M7	VSS	power_in	0 V general device ground.
M8	VSS	power_in	0 V general device ground.
M9	VSS	power_in	0 V general device ground.
M10	VSS	power_in	0 V general device ground.
M11	VSS	power_in	0 V general device ground.
M12	VDD12	power_in	1.2 V supply for the internal digital logic.
M13	VDD33	power_in	General 3.3 V power supply.
M14	GPIO1/SIGDET1	bidirectional	General-purpose input/output that can also serve as the SIGDET input for PHY port 1 if not used as GPIO.
M15	GPIO2/SIGDET2	bidirectional	General-purpose input/output that can also serve as the SIGDET input for PHY port 2 if not used as GPIO.
M16	GPIO3/SIGDET3	bidirectional	General-purpose input/output that can also serve as the SIGDET input for PHY port 3 if not used as GPIO.
N1	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
N2	MDIO	bidirectional	Management data input/output, clocked on the positive edge of MDC; datasheet lists it as open-drain and requires one external pull-up resistor at the station manager (2 kΩ per Section 3.13).
N3	MDINT1	output	Management interrupt output for PHY 1, configured as active-low open-drain or active-high open-source by an external resistor at reset.
N4	MDINT2	output	Management interrupt output for PHY 2, configured as active-low open-drain or active-high open-source by an external resistor at reset.
N5	VDD12	power_in	1.2 V supply for the internal digital logic.
N6	VSS	power_in	0 V general device ground.
N7	VSS	power_in	0 V general device ground.
N8	VSS	power_in	0 V general device ground.
N9	VSS	power_in	0 V general device ground.
N10	VSS	power_in	0 V general device ground.
N11	VSS	power_in	0 V general device ground.
N12	VDD12	power_in	1.2 V supply for the internal digital logic.
N13	VSS	power_in	0 V general device ground.
N14	GPIO0/SIGDET0	bidirectional	General-purpose input/output that can also serve as the SIGDET input for PHY port 0 if not used as GPIO.
N15	TDP_0	input	SerDes MAC transmitter input pair, positive leg, for PHY 0 (IDIFF).
N16	TDN_0	input	SerDes MAC transmitter input pair, negative leg, for PHY 0 (IDIFF).
P1	RESERVED	unconnected	Reserved pin; leave unconnected (floating).
P2	MDC	input	Management data clock input, 0 MHz to 12.5 MHz, used to clock MDIO data in and out of the PHY.
P3	VDDIO	power_in	I/O power supply for MDC, MDIO, MDINTn and NRESET, selectable at 3.3 V, 2.5 V or 1.8 V.
P4	VSS	power_in	0 V general device ground.
P5	VDD33	power_in	General 3.3 V power supply.
P6	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P7	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P8	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P9	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P10	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P11	VDD12A	power_in	1.2 V analog power supply requiring additional PCB power supply filtering.
P12	VDD33	power_in	General 3.3 V power supply.
P13	VDD33	power_in	General 3.3 V power supply.
P14	VSS	power_in	0 V general device ground.
P15	RDP_0	output	SerDes MAC receiver output pair, positive leg, for PHY 0 (ODIFF).
P16	RDN_0	output	SerDes MAC receiver output pair, negative leg, for PHY 0 (ODIFF).
R1	VSS	power_in	0 V general device ground.
R2	FIBR_DOP_3	output	SerDes media transmitter output pair, positive leg, for PHY 3 (ODIFF).
R3	FIBR_DIP_3	input	SerDes media receiver input pair, positive leg, for PHY 3 (IDIFF).
R4	RDP_3	output	SerDes MAC receiver output pair, positive leg, for PHY 3 (ODIFF).
R5	TDP_3	input	SerDes MAC transmitter input pair, positive leg, for PHY 3 (IDIFF).
R6	FIBR_DOP_2	output	SerDes media transmitter output pair, positive leg, for PHY 2 (ODIFF).
R7	FIBR_DIP_2	input	SerDes media receiver input pair, positive leg, for PHY 2 (IDIFF).
R8	RDP_2	output	SerDes MAC receiver output pair, positive leg, for PHY 2 (ODIFF).
R9	TDP_2	input	SerDes MAC transmitter input pair, positive leg, for PHY 2 (IDIFF).
R10	FIBR_DOP_1	output	SerDes media transmitter output pair, positive leg, for PHY 1 (ODIFF).
R11	FIBR_DIP_1	input	SerDes media receiver input pair, positive leg, for PHY 1 (IDIFF).
R12	RDP_1	output	SerDes MAC receiver output pair, positive leg, for PHY 1 (ODIFF).
R13	TDP_1	input	SerDes MAC transmitter input pair, positive leg, for PHY 1 (IDIFF).
R14	FIBR_DOP_0	output	SerDes media transmitter output pair, positive leg, for PHY 0 (ODIFF).
R15	FIBR_DIP_0	input	SerDes media receiver input pair, positive leg, for PHY 0 (IDIFF).
R16	VSS	power_in	0 V general device ground.
T1	NC	unconnected	No-connect ball; leave floating and do not connect it to other pins or ground.
T2	FIBR_DON_3	output	SerDes media transmitter output pair, negative leg, for PHY 3 (ODIFF).
T3	FIBR_DIN_3	input	SerDes media receiver input pair, negative leg, for PHY 3 (IDIFF).
T4	RDN_3	output	SerDes MAC receiver output pair, negative leg, for PHY 3 (ODIFF).
T5	TDN_3	input	SerDes MAC transmitter input pair, negative leg, for PHY 3 (IDIFF).
T6	FIBR_DON_2	output	SerDes media transmitter output pair, negative leg, for PHY 2 (ODIFF).
T7	FIBR_DIN_2	input	SerDes media receiver input pair, negative leg, for PHY 2 (IDIFF).
T8	RDN_2	output	SerDes MAC receiver output pair, negative leg, for PHY 2 (ODIFF).
T9	TDN_2	input	SerDes MAC transmitter input pair, negative leg, for PHY 2 (IDIFF).
T10	FIBR_DON_1	output	SerDes media transmitter output pair, negative leg, for PHY 1 (ODIFF).
T11	FIBR_DIN_1	input	SerDes media receiver input pair, negative leg, for PHY 1 (IDIFF).
T12	RDN_1	output	SerDes MAC receiver output pair, negative leg, for PHY 1 (ODIFF).
T13	TDN_1	input	SerDes MAC transmitter input pair, negative leg, for PHY 1 (IDIFF).
T14	FIBR_DON_0	output	SerDes media transmitter output pair, negative leg, for PHY 0 (ODIFF).
T15	FIBR_DIN_0	input	SerDes media receiver input pair, negative leg, for PHY 0 (IDIFF).
T16	NC	unconnected	No-connect ball; leave floating and do not connect it to other pins or ground.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	BGA-256(17x17)
Category	Interface ICs
Pins	256

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply voltage for VDDIO at 1.8 V	VDDIO	1.7	1.8	1.9	V		85
Power supply voltage for VDDIO at 2.5 V	VDDIO	2.37	2.5	2.63	V		85
Power supply voltage for VDDIO at 3.3 V	VDDIO	3.13	3.3	3.47	V		85
Power supply voltage for VDD33	VDD33	3.13	3.3	3.47	V		85
Power supply voltage for VDD12	VDD12	1.14	1.2	1.26	V		85
Power supply voltage for VDD12A	VDD12A	1.14	1.2	1.26	V		85
VSC8664 operating temperature	T	0		90	°C	Lower limit ambient, upper limit case (VSC8664XIC)	85
DC input voltage on VDDIO supply pin	VDDIO	-0.5		4	V		85
DC input voltage on VDD33 supply pin	VDD33	-0.5		4	V		85
DC input voltage on VDD12 supply pin	VDD12	-0.5		1.4	V		85
DC input voltage on VDD12A supply pin	VDD12A	-0.5		1.4	V		85
DC input voltage on JTAG 5 V-tolerant pins	VDD(5 V)	-0.5		5.5	V		85
DC input voltage on any non-supply pin	VDD(PIN)	-0.5			V	Printed maximum is VDD + 0.5 V (not numeric)	85
Storage temperature	TS	-65		150	°C		85
Electrostatic discharge voltage, charged device model	VESD_CDM	-500		500	V		85
Output high voltage (VDD33 at 3.30 V)	VOH	2.4		3.6	V	IOH = -4 mA	76
Output low voltage (VDD33 at 3.30 V)	VOL	0		0.5	V	IOL = 4 mA	76
Input high voltage (VDD33 at 3.30 V)	VIH	2.1		3.6	V		77
Input low voltage (VDD33 at 3.30 V)	VIL	-0.3		0.9	V		77
Output high voltage (VDDIO at 3.3 V)	VOH	2.4		3.6	V	IOH = -4 mA	75
Output low voltage (VDDIO at 3.3 V)	VOL	0		0.5	V	IOL = 4 mA	75
Input high voltage (VDDIO at 3.3 V)	VIH	2.1		3.6	V		75
Input low voltage (VDDIO at 3.3 V)	VIL	-0.3		0.9	V		75
Output high voltage (VDDIO at 2.5 V)	VOH	2		2.8	V	IOH = -1.0 mA	75
Output low voltage (VDDIO at 2.5 V)	VOL	-0.3		0.4	V	IOL = 1.0 mA	75
Input high voltage (VDDIO at 2.5 V)	VIH	1.7		3	V		76
Input low voltage (VDDIO at 2.5 V)	VIL	-0.3		0.7	V		76
Output high voltage (VDDIO at 1.8 V)	VOH	1.4		2.1	V	IOH = -0.5 mA	76
Output low voltage (VDDIO at 1.8 V)	VOL			0.3	V	IOL = 0.5 mA	76
Input high voltage (VDDIO at 1.8 V)	VIH	1.2		2.1	V		76
Input low voltage (VDDIO at 1.8 V)	VIL			0.6	V		76
Output differential voltage (MAC_RDP/N_n, FIBR_DOP/N_n)	VODIFF	700	1000	1200	mV	Measured peak-to-peak. Based on 100 Ω differential load.	77
Output common-mode voltage (MAC_RDP/N_n, FIBR_DOP/N_n)	VOCM	480	540	610	mV	VDD12A = 1.20 V.	77
Input differential voltage (MAC_TDP/N_n, FIBR_DIP/N_n)	VIDIFF	120		2400	mV	Measured peak-to-peak. Based on 100 Ω differential load.	77
Input common mode voltage (MAC_TDP/N_n, FIBR_DIP/N_n)	VICM	0.4		1.3	V	VDD12A = 1.20 V.	77
Output high voltage (LED[3:0]_n)	VOH	2.4		3.6	V	IOH = -4.0 mA	78
Output low voltage (LED[3:0]_n)	VOL	0		0.5	V	IOL = 4.0 mA	78
Output high voltage (JTAG pins)	VOH	2.4		3.6	V	IOH = -1.5 mA	78
Output low voltage (JTAG pins)	VOL	0		0.5	V	IOL = 1.5 mA	78
Input high voltage (JTAG pins)	VIH	2.1		3.6	V		78
Input low voltage (JTAG pins)	VIL	-0.3		0.9	V		78
Worst-case power consumption	PD			3.19	W	Typical Maximum column; single value printed, assigned to max	79
Current with VDDIO at 3.3 V	IVDDIO			1	mA	Typical Maximum column; single value printed, assigned to max	79
Current with VDD33 at 3.3 V	IVDD33			460	mA	Typical Maximum column; single value printed, assigned to max	79
Current with VDD12 at 1.2 V	IVDD12			774	mA	Typical Maximum column; single value printed, assigned to max	79
Current with VDD12A at 1.2 V	IVDD12A			273	mA	Typical Maximum column; single value printed, assigned to max	79
Frequency stability (REFCLK input frequency accuracy)	fTOL			100	ppm		80
REFCLK duty cycle	%DUTY	40		60	%		80
CLKOUT duty cycle	%DUTY	40	50	60	%		80
RCVRD_CLK duty cycle	%DUTY	45	50	55	%		81
Total jitter for 1000BASE-T (RCVRD_CLK)	JCLK		325	400	ps	Measured peak-to-peak	81
Total receive jitter tolerance (MAC_TDP/N_n, FIBR_DIP/N_n)	JRXTotal			610	ps	Measured peak-to-peak. 1000BASE-X mode.	82
MDC frequency	fCLK	2.5		12.5	MHz		83
NRESET assertion time	tRESET	100			ns		83
Thermal resistance junction-to-case	θJC		7.5		°C/W		103
Thermal resistance junction-to-board	θJB		11.2		°C/W		103
Thermal resistance junction-to-ambient	θJA		21.9		°C/W	0 ft/min airflow	103
Thermal resistance junction-to-ambient	θJA		20.4		°C/W	100 ft/min airflow	103
Thermal resistance junction-to-ambient	θJA		19.4		°C/W	200 ft/min airflow	103

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		(BGA) with a 17 mm × 17 mm body size, 1 mm pin pitch, and 2 mm maximum height. Lead-free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and	101
contacts	copper		• Supports 100BASE-FX fiber, 1000BASE-X fiber, and triple-speed copper SFPs over SerDes pins	13

CAD (KiCad official)

Symbol: VSC8664XIC
Footprint: Package_BGA:BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD
3D model: BGA-256(17x17) (KiCad packages3D, STEP)
3D model files: vsc8664xic-etched.step / vsc8664xic-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsc8664xic.step / vsc8664xic.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (108 pp, sha256 9cf43c1020671c57, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

VSC8664XIC

Changed since verified VSC8664XIC

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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