VSC8531XMW-05 from Microchip Tech, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD25A	power_in	2.5 V analog power supply, requiring additional PCB power supply filtering; recommended range 2.38 V to 2.62 V.
2	VDD1A	power_in	1.0 V analog power supply, requiring additional PCB power supply filtering; recommended range 0.95 V to 1.05 V.
3	P0_D3N	passive	Cu PHY media Tx/Rx channel D negative signal (analog differential pair, VDD25A domain).
4	P0_D3P	passive	Cu PHY media Tx/Rx channel D positive signal (analog differential pair, VDD25A domain).
5	VDD25A	power_in	2.5 V analog power supply, requiring additional PCB power supply filtering; recommended range 2.38 V to 2.62 V.
6	P0_D2N	passive	Cu PHY media Tx/Rx channel C negative signal (analog differential pair, VDD25A domain).
7	P0_D2P	passive	Cu PHY media Tx/Rx channel C positive signal (analog differential pair, VDD25A domain).
8	VDD25A	power_in	2.5 V analog power supply, requiring additional PCB power supply filtering; recommended range 2.38 V to 2.62 V.
9	P0_D1N	passive	Cu PHY media Tx/Rx channel B negative signal (analog differential pair, VDD25A domain).
10	P0_D1P	passive	Cu PHY media Tx/Rx channel B positive signal (analog differential pair, VDD25A domain).
11	P0_D0N	passive	Cu PHY media Tx/Rx channel A negative signal (analog differential pair, VDD25A domain).
12	P0_D0P	passive	Cu PHY media Tx/Rx channel A positive signal (analog differential pair, VDD25A domain).
13	VDD1A	power_in	1.0 V analog power supply, requiring additional PCB power supply filtering; recommended range 0.95 V to 1.05 V.
14	VDD1	power_in	1.0 V digital core power; recommended range 0.95 V to 1.05 V.
15	VDDMAC	power_in	RGMII/RMII MAC power supply at 1.5 V, 1.8 V, 2.5 V, or 3.3 V; recommended range 1.425 V to 3.465 V depending on selected level.
16	RXD3	bidirectional	RGMII receive data output bit 3 (RMII/RGMII shared pin, VDDMAC domain); its logic state is latched on the rising edge of NRESET for configuration.
17	RXD2	bidirectional	RGMII receive data output bit 2 (RMII/RGMII shared pin, VDDMAC domain); its logic state is latched on the rising edge of NRESET for configuration.
18	RXD1	bidirectional	RGMII receive data output bit 1 (RMII/RGMII shared pin, VDDMAC domain); its logic state is latched on the rising edge of NRESET for configuration.
19	VDDMAC	power_in	RGMII/RMII MAC power supply at 1.5 V, 1.8 V, 2.5 V, or 3.3 V; recommended range 1.425 V to 3.465 V depending on selected level.
20	RXD0	bidirectional	RGMII receive data output bit 0 (RMII/RGMII shared pin, VDDMAC domain); its logic state is latched on the rising edge of NRESET for configuration.
21	RX_CTL	bidirectional	RGMII receive control output (RMII/RGMII shared pin, VDDMAC domain); its logic state is latched on the rising edge of NRESET for configuration.
22	RX_CLK	bidirectional	RGMII receive clock output (carries RMII_CLKOUT in RMII mode, 50 MHz); its logic state is latched on the rising edge of NRESET for configuration.
23	TX_CTL	input	RGMII transmit data control input (VDDMAC domain, internal pull-down).
24	VDD1	power_in	1.0 V digital core power; recommended range 0.95 V to 1.05 V.
25	TX_CLK	input	RGMII transmit clock input (VDDMAC domain, internal pull-down).
26	TXD0	input	RGMII data input bit 0 (VDDMAC domain, internal pull-down).
27	VDDMAC	power_in	RGMII/RMII MAC power supply at 1.5 V, 1.8 V, 2.5 V, or 3.3 V; recommended range 1.425 V to 3.465 V depending on selected level.
28	TXD1	input	RGMII data input bit 1 (VDDMAC domain, internal pull-down).
29	TXD2	input	RGMII data input bit 2 (VDDMAC domain, internal pull-down).
30	TXD3	input	RGMII data input bit 3 (VDDMAC domain, internal pull-down).
31	MDC	input	Management data clock reference input for the SMI, 0 MHz to 12.5 MHz, referenced to VDDMDIO.
32	VDDMDIO	power_in	Power for SMI pins at 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V; recommended range 1.14 V to 3.465 V depending on selected level.
33	MDIO	bidirectional	Management data input/output, synchronous to the positive edge of MDC; requires one external pull-up resistor at the station manager.
34	MDINT	output	Management interrupt, open-drain output that can be wired-OR with other MDINT pins using a single pull-up resistor.
35	NRESET	input	Active-low device reset input that powers down the device and sets all register bits to default; the NRESET pulse width must be at least 100 ns.
36	CLKOUT	bidirectional	Programmable-frequency clock output (125, 50 or 25 MHz) derived from the reference clock, disabled and held low by default and inactive while NRESET is asserted.
37	VDDIO	power_in	2.5 V or 3.3 V general I/O power; recommended range 2.38 V to 3.465 V depending on selected level.
38	LED1	output	Active-low LED direct drive output; carries LED_CLK in serial LED mode.
39	LED0	output	Active-low LED direct drive output; carries LED_DATA in serial LED mode.
40	REFCLK_SEL_1	input	Reference clock mode/frequency select input with internal pull-up, referenced to VDDIO.
41	REFCLK_SEL_0	input	Reference clock mode/frequency select input with internal pull-up, referenced to VDDIO.
42	XTAL1	input	Crystal or single-ended reference clock input, referenced to VDD25A.
43	XTAL2	output	Crystal output; leave unconnected when using a single-ended reference clock.
44	RESERVED_1	unconnected	Reserved signal; leave unconnected.
45	RESERVED_0	unconnected	Reserved signal; leave unconnected.
46	REF_FILT	passive	Reference filter; connect to an external 0.01 µF (20%) capacitor to analog ground.
47	VDD1A	power_in	1.0 V analog power supply, requiring additional PCB power supply filtering; recommended range 0.95 V to 1.05 V.
48	REF_REXT	passive	Reference resistor connection; connect to an external 2 kΩ (1%) resistor to analog ground.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-48-EP(6x6)
Category	Interface ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply voltage for core supply	VDD1	0.95	1	1.05	V		73
Power supply voltage for analog circuits	VDD1A	0.95	1	1.05	V		73
2.5 V power supply voltage for analog circuits	VDD25A	2.38	2.5	2.62	V		73
2.5 V power supply voltage for VDDMAC, VDDIO, and VDDMDIO	V25	2.38	2.5	2.62	V		73
3.3 V power supply voltage for VDDMAC, VDDIO, and VDDMDIO	V33	3.135	3.3	3.465	V		74
1.8 V power supply voltage for VDDMAC and VDDMDIO	V18	1.71	1.8	1.89	V		74
1.5 V power supply voltage for VDDMAC and VDDMDIO	V15	1.425	1.5	1.575	V		74
1.2 V power supply voltage for VDDMDIO	V12	1.14	1.2	1.26	V		74
VSC8531-05 operating temperature	T	-40		125	°C	VSC8531-05; minimum ambient, maximum junction	74
Power supply voltage for core supply	VDD1	-0.3		1.1	V		74
Power supply voltage for analog circuits	VDD1A	-0.3		1.1	V		74
Power supply voltage for analog circuits	VDD25A	-0.3		2.75	V		74
Power supply voltage for digital I/O VDDMAC, VDDIO, VDDMDIO		-0.3		3.6	V		74
Input voltage for digital I/O (3.3 V)				3.6	V	3.3 V	74
Input voltage for digital I/O (2.5 V)				3.3	V	2.5 V	74
Storage temperature	TS	-55		125	°C		74
Output high voltage (2.5 V)	VOH	2			V	IOH = -1.0 mA	64
Output low voltage (2.5 V)	VOL			0.4	V	IOL = 1.0 mA	64
Input high voltage (2.5 V)	VIH	1.85		3.6	V		64
Input low voltage (2.5 V)	VIL	-0.3		0.7	V		64
Input leakage current (2.5 V)	IILEAK	-85		85	µA	Internal resistor included	64
Output high voltage (3.3 V)	VOH	2.6			V	IOH = -1.0 mA	64
Output low voltage (3.3 V)	VOL			0.4	V	IOL = 1.0 mA	64
Input high voltage (3.3 V)	VIH	2.25		3.6	V		64
Input low voltage (3.3 V)	VIL	-0.3		0.8	V		64
Input leakage current (3.3 V)	IILEAK	-135		135	µA	Internal resistor included	64
Output high voltage (1.5 V)	VOH	1.2			V	IOH = -1 mA	65
Output low voltage (1.5 V)	VOL			0.25	V	IOL = 1 mA	65
Input high voltage (1.5 V) VDDMDIO-referenced pins	VIH	1.13		1.87	V	VDDMDIO-referenced pins	65
Input high voltage (1.5 V) VDDMAC-referenced pins	VIH	1.13		1.65	V	VDDMAC-referenced pins	65
Input low voltage (1.5 V)	VIL	-0.375		0.45	V		65
Input leakage current (1.5 V)	IILEAK	-40		40	µA	Internal resistor included	65
Output high voltage (1.8 V)	VOH	1.43			V	IOH = -1 mA	65
Output low voltage (1.8 V)	VOL			0.3	V	IOL = 1 mA	65
Input high voltage (1.8 V) VDDMDIO-referenced pins	VIH	1.35		2.25	V	VDDMDIO-referenced pins	65
Input high voltage (1.8 V) VDDMAC-referenced pins	VIH	1.35		1.98	V	VDDMAC-referenced pins	65
Input low voltage (1.8 V)	VIL	-0.45		0.54	V		65
Input leakage current (1.8 V)	IILEAK	-48		48	µA	Internal resistor included	65
Output high voltage (VDDMDIO 1.2 V)	VOH	0.95			V	IOH = -1 mA	65
Output low voltage (VDDMDIO 1.2 V)	VOL			0.2	V	IOL = 1 mA	65
Input high voltage (VDDMDIO 1.2 V)	VIH	0.9		1.5	V		65
Input low voltage (VDDMDIO 1.2 V)	VIL	-0.3		0.36	V		65
Input leakage current (VDDMDIO 1.2 V)	IILEAK	-32		32	µA	Internal resistor included	65
XTAL1 input high voltage	VIH	1.85		2.75	V	XTAL1 referenced to VDD25A	66
XTAL1 input low voltage	VIL	-0.3		0.7	V	XTAL1 referenced to VDD25A	66
Internal pull-down resistor (RGMII/RMII, 3.3 V)	RPD	31	46	72	kΩ	3.3 V	66
Internal pull-down resistor (RGMII/RMII, 2.5 V)	RPD	38	59	96	kΩ	2.5 V	66
Internal pull-down resistor (RGMII/RMII, 1.8 V)	RPD	57	91	155	kΩ	1.8 V	66
Internal pull-down resistor (RGMII/RMII, 1.5 V)	RPD	78	125	220	kΩ	1.5 V	66
REFCLK frequency tolerance	ƒ	-100		100	ppm	REFCLK_SEL[1:0]= 11, nominal 125 MHz	68
Worst-case power consumption	PD			980	mW		67
Current consumption VDD25A, 1000BASE-T			150		mA	1000BASE-T mode	67
Die junction to package case top	θJCtop		31.62		°C/W		82
Die junction to printed circuit board	θJB		9.34		°C/W		82
Die junction to ambient	θJA		31.73		°C/W		82
Die junction to moving air	θJMA		25		°C/W	air speed 1 m/s	82
Die junction to moving air	θJMA		23.75		°C/W	air speed 2 m/s	82

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	PC		with an exposed pad, 6 mm × 6 mm body size, 0.4 mm pin pitch, and 0.9 mm maximum height. Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC	80
contacts	copper		enabled or disabled for each LED pin. For example, a copper link running in 1000BASE-T mode and	27

CAD (KiCad official)

Symbol: VSC8531XMW-05
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: QFN-48-EP(6x6) (KiCad packages3D, STEP)
3D model files: vsc8531xmw-05-etched.step / vsc8531xmw-05-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsc8531xmw-05.step / vsc8531xmw-05.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (85 pp, sha256 73781f7b86d5935c, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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VSC8531XMW-05

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