component
VS6662GS
Public Made by Adomby adom
Vergiga(威兆) , SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 3d ago |
| package.json | 3d ago |
| page.json | 3d ago |
| README.md | 3d ago |
| vs6662gs-etched.glb | 3d ago |
| vs6662gs-etched.step | 3d ago |
| vs6662gs-hero.glb | 3d ago |
| vs6662gs-hero.overlay.json | 3d ago |
| vs6662gs.glb | 3d ago |
| vs6662gs.kicad_mod | 3d ago |
| vs6662gs.kicad_sym | 3d ago |
| vs6662gs.lbr | 3d ago |
| vs6662gs.step | 3d ago |
VS6662GS
Vergiga(威兆) · IC · SOP-8
VS6662GS from Vergiga(威兆), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET (Source pins 1-3); drain-source rated 60 V, continuous current 13 A at TA=25°C. |
| 2 | S | passive | Source terminal of the N-channel MOSFET (Source pins 1-3); drain-source rated 60 V, continuous current 13 A at TA=25°C. |
| 3 | S | passive | Source terminal of the N-channel MOSFET (Source pins 1-3); drain-source rated 60 V, continuous current 13 A at TA=25°C. |
| 4 | G | input | Gate terminal, gate-source voltage limited to ±20 V with threshold of 1.3 V min to 2.4 V max at 250 µA. |
| 5 | D | passive | Drain terminal (Drain pins 5-8); V(BR)DSS 60 V minimum, RDS(on) 6.5 mΩ typ at VGS=10V. |
| 6 | D | passive | Drain terminal (Drain pins 5-8); V(BR)DSS 60 V minimum, RDS(on) 6.5 mΩ typ at VGS=10V. |
| 7 | D | passive | Drain terminal (Drain pins 5-8); V(BR)DSS 60 V minimum, RDS(on) 6.5 mΩ typ at VGS=10V. |
| 8 | D | passive | Drain terminal (Drain pins 5-8); V(BR)DSS 60 V minimum, RDS(on) 6.5 mΩ typ at VGS=10V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vergiga(威兆) |
| Package | SOP-8 |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Gate-Source voltage | VGS | -20 | 20 | V | 1 | ||
| Diode continuous forward current | IS | 13 | A | TA = 25°C | 1 | ||
| Continuous drain current (silicon limited) | ID | 13 | A | VGS=10V, TA = 25°C | 1 | ||
| Continuous drain current (silicon limited) | ID | 10 | A | VGS=10V, TA = 70°C | 1 | ||
| Pulse drain current tested | IDM | 52 | A | TA = 70°C; single pulse, pulse width ≤ 100μs (note ①) | 1 | ||
| Avalanche energy, single pulsed | EAS | 25 | mJ | TJ start 25°C, L = 0.5mH, RG = 25Ω, IAS = 10A, VGS = 10V (note ②) | 1 | ||
| Maximum power dissipation | PD | 2.5 | W | TA = 25°C | 1 | ||
| Maximum power dissipation | PD | 1.6 | W | TA = 70°C | 1 | ||
| Storage and junction temperature range | TSTG,TJ | -55 | 150 | °C | 1 | ||
| Thermal resistance, junction-to-lead | RθJL | 24 | 29 | °C/W | 1 | ||
| Thermal resistance, junction-to-ambient | RθJA | 42 | 50 | °C/W | t≤10s | 1 | |
| Thermal resistance, junction-to-ambient | RθJA | 75 | 90 | °C/W | Steady State | 1 | |
| Drain-Source breakdown voltage | V(BR)DSS | 60 | V | VGS=0V, ID=250μA | 2 | ||
| Zero gate voltage drain current (Tj=25℃) | IDSS | 1 | μA | VDS=60V, VGS=0V | 2 | ||
| Zero gate voltage drain current (Tj=125℃) | IDSS | 100 | μA | VDS=60V, VGS=0V | 2 | ||
| Gate-Body leakage current | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 2 | |
| Gate threshold voltage | VGS(th) | 1.3 | 1.75 | 2.4 | V | VDS=VGS, ID=250μA | 2 |
| Drain-Source on-state resistance | RDS(on) | 6.5 | 8.5 | mΩ | VGS=10V, ID=10A | 2 | |
| Drain-Source on-state resistance | RDS(on) | 9.5 | 12 | mΩ | VGS=4.5V, ID=8A | 2 | |
| Input capacitance | Ciss | 525 | 1050 | 1840 | pF | VDS=30V, VGS=0V, f=1MHz | 2 |
| Output capacitance | Coss | 170 | 345 | 600 | pF | VDS=30V, VGS=0V, f=1MHz | 2 |
| Reverse transfer capacitance | Crss | 15 | 35 | 65 | pF | VDS=30V, VGS=0V, f=1MHz | 2 |
| Gate resistance | Rg | 0.2 | 0.8 | 5 | Ω | f=1MHz | 2 |
| Total gate charge | Qg(10V) | 22 | 39 | nC | VDS=30V, ID=10A, VGS=10V | 2 | |
| Total gate charge | Qg(4.5V) | 12 | 21 | nC | 2 | ||
| Gate-Source charge | Qgs | 3.2 | 5.6 | nC | 2 | ||
| Gate-Drain charge | Qgd | 5.8 | 10 | nC | 2 | ||
| Forward on voltage | VSD | 0.8 | 1.2 | V | ISD=10A, VGS=0V | 2 | |
| Reverse recovery time | Trr | 23 | 46 | ns | Isd=10A, VGS=0V, di/dt=100A/μs | 2 | |
| Reverse recovery charge | Qrr | 11 | 22 | nC | 2 |
CAD (KiCad official)
- Symbol:
VS6662GS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
vs6662gs-etched.step/vs6662gs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vs6662gs.step/vs6662gs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vergiga(威兆) datasheet (7 pp, sha256
7a398fcf59802a90, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).