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Contents

README

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VS4603DM6

Vergiga(威兆) · IC · TO-263-6

VS4603DM6 from Vergiga(威兆), in a TO-263-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; Gate-Source voltage limited to ±20 V, threshold 1.3 to 2.4 V at VDS=VGS, ID=250μA.
2 S passive Source; pins 2, 3, 4, 5, 6 are all source, continuous current 175 A (wire bond limited) at TC=25°C.
3 S passive Source; pins 2, 3, 4, 5, 6 are all source, continuous current 175 A (wire bond limited) at TC=25°C.
4 S passive Source; pins 2, 3, 4, 5, 6 are all source, continuous current 175 A (wire bond limited) at TC=25°C.
5 S passive Source; pins 2, 3, 4, 5, 6 are all source, continuous current 175 A (wire bond limited) at TC=25°C.
6 S passive Source; pins 2, 3, 4, 5, 6 are all source, continuous current 175 A (wire bond limited) at TC=25°C.
7 D passive Drain (Tab); drain-source breakdown voltage 40 V, pulsed drain current 1100 A at TC=25°C.

Key specifications

Parameter Value
Manufacturer Vergiga(威兆)
Package TO-263-6
Category
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate-Source voltage VGS -20 20 V 1
Diode continuous forward current (wire bond limited) IS 175 A TC = 25°C 1
Continuous drain current (wire bond limited) ID 175 A @VGS=10V, TC = 25°C 1
Pulse drain current tested IDM 1100 A TC = 25°C 1
Continuous drain current IDSM 33 A @VGS=10V, TA = 25°C 1
Continuous drain current IDSM 26 A @VGS=10V, TA = 70°C 1
Avalanche energy, single pulsed EAS 506 mJ single pulsed ② 1
Maximum power dissipation PD 300 W TC = 25°C 1
Maximum power dissipation PDSM 2 W TA = 25°C 1
Storage and junction temperature range TSTG,TJ -55 175 °C 1
Thermal resistance, junction-to-case RθJC 0.5 1 °C/W 1
Thermal resistance, junction-to-ambient RθJA 62.5 75 °C/W 1
Drain-source breakdown voltage V(BR)DSS 40 V VGS=0V, ID=250μA 2
Zero gate voltage drain current (Tj=25℃) IDSS 1 μA VDS=40V, VGS=0V 2
Zero gate voltage drain current (Tj=125℃) IDSS 100 μA VDS=40V, VGS=0V 2
Gate-body leakage current IGSS -100 100 nA VGS=±20V, VDS=0V 2
Gate threshold voltage VGS(th) 1.3 1.8 2.4 V VDS=VGS, ID=250μA 2
Drain-source on-state resistance RDS(on) 1.1 1.4 mΩ VGS=10V, ID=60A 2
Drain-source on-state resistance RDS(on) 1.5 2 mΩ VGS=4.5V, ID=40A 2
Input capacitance Ciss 11410 15210 20230 pF VDS=20V, VGS=0V, f=1MHz 2
Output capacitance Coss 930 1245 1655 pF VDS=20V, VGS=0V, f=1MHz 2
Reverse transfer capacitance Crss 580 770 1025 pF VDS=20V, VGS=0V, f=1MHz 2
Gate resistance Rg 0.2 0.5 3 Ω f=1MHz 2
Total gate charge Qg(10V) 204 271 nC VDS=20V, ID=60A, VGS=10V 2
Total gate charge Qg(4.5V) 97 129 nC VDS=20V, ID=60A, VGS=10V 2
Gate-source charge Qgs 45 60 nC VDS=20V, ID=60A, VGS=10V 2
Gate-drain charge Qgd 38 57 nC VDS=20V, ID=60A, VGS=10V 2
Forward on voltage VSD 0.8 1.2 V ISD=40A, VGS=0V 2
Reverse recovery time Trr 31 62 ns Isd=60A, VGS=0V, di/dt=100A/μs 2
Reverse recovery charge Qrr 28 56 nC Isd=60A, VGS=0V, di/dt=100A/μs 2

CAD (KiCad official)

  • Symbol: VS4603DM6
  • Footprint: Package_TO_SOT_SMD:TO-263-6
  • 3D model: TO-263-6 (KiCad packages3D, STEP)
  • 3D model files: vs4603dm6-etched.step / vs4603dm6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vs4603dm6.step / vs4603dm6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vergiga(威兆) datasheet (7 pp, sha256 dea9c17ee140963c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF