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VS1401ATH

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Vergiga(威兆) , TO-220AB. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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VS1401ATH

Vergiga(威兆) · IC · TO-220AB

VS1401ATH from Vergiga(威兆), in a TO-220AB. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate; enhancement-mode control input with a maximum gate-source voltage of ±25 V and a typical threshold of 3 V (2.4 to 3.6 V) at 250 µA.
2 D passive Drain, also connected to the mounting tab; 100 V drain-source breakdown, 130 A package-limited continuous current.
3 S passive Source; carries up to 130 A package-limited continuous current, and the body diode conducts up to 200 A continuous forward current.

Key specifications

Parameter Value
Manufacturer Vergiga(威兆)
Package TO-220AB
Category
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage V(BR)DSS 100 V VGS=0V, ID=250μA 2
Zero Gate Voltage Drain Current IDSS 1 μA VDS=100V,VGS=0V 2
Zero Gate Voltage Drain Current (Tj=125℃) IDSS 100 μA Tj =125℃, VDS=100V,VGS=0V 2
Gate-Body Leakage Current IGSS -100 100 nA VGS=±25V,VDS=0V 2
Gate Threshold Voltage VGS(th) 2.4 3 3.6 V VDS=VGS,ID=250μA 2
Drain-Source On-State Resistance RDS(on) 4.5 5.5 mΩ VGS=10V, ID=80A 2
Input Capacitance Ciss 11065 14755 19625 pF VDS=30V,VGS=0V, f=1MHz 2
Output Capacitance Coss 500 665 885 pF VDS=30V,VGS=0V, f=1MHz 2
Reverse Transfer Capacitance Crss 370 495 660 pF VDS=30V,VGS=0V, f=1MHz 2
Gate Resistance Rg 0.2 2.3 5 Ω f=1MHz 2
Total Gate Charge Qg 232 309 nC VDS=50V,ID=40A,VGS=10V 2
Gate-Source Charge Qgs 59 78 nC VDS=50V,ID=40A,VGS=10V 2
Gate-Drain Charge Qgd 60 90 nC VDS=50V,ID=40A,VGS=10V 2
Forward on voltage VSD 0.9 1.2 V ISD=80A,VGS=0V 2
Reverse Recovery Time Trr 44 88 ns Tj=25℃,Isd=40A,VGS=0V, di/dt=100A/μs 2
Reverse Recovery Charge Qrr 77 154 nC Tj=25℃,Isd=40A,VGS=0V, di/dt=100A/μs 2
Gate-Source Voltage VGS -25 25 V 1
Diode continuous forward current IS 200 A TC = 25°C 1
Continuous drain current (Silicon limited) ID 200 A @VGS=10V, TC = 25°C 1
Continuous drain current (Silicon limited) ID 142 A @VGS=10V, TC = 100°C 1
Continuous drain current (Wire bond limited) ID 130 A @VGS=10V, TC = 25°C 1
Pulse drain current IDM 800 A TC =25°C 1
Continuous drain current (TA) IDSM 15 A @VGS=10V, TA=25°C 1
Continuous drain current (TA) IDSM 12 A @VGS=10V, TA=70°C 1
Avalanche energy, single pulsed EAS 900 mJ 1
Maximum power dissipation PD 375 W TC =25°C 1
Maximum power dissipation PDSM 2 W TA=25°C 1
Storage and Junction Temperature Range TSTG,TJ -55 175 °C 1
Thermal Resistance, Junction-to-Case RθJC 0.4 0.5 °C/W 1
Thermal Resistance, Junction-to-Ambient RθJA 62.5 75 °C/W 1

CAD (KiCad official)

  • Symbol: VS1401ATH
  • Footprint: Package_TO_SOT_THT:TO-220-3_Vertical
  • 3D model: TO-220AB (KiCad packages3D, STEP)
  • 3D model files: vs1401ath-etched.step / vs1401ath-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vs1401ath.step / vs1401ath.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vergiga(威兆) datasheet (7 pp, sha256 2a20c98480d9dd95, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF