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Contents

README

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VS1000D-L

VLSI Solution · Audio Interface ICs · LQFP-48(7x7)

VS1000D-L from VLSI Solution, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XRESET input Active low asynchronous reset, schmitt-trigger input.
2 NFDIO0/GPIO0_0 bidirectional NAND-flash IO0 / General-purpose IO Port 0, bit 0.
3 NFDIO1/GPIO0_1 bidirectional NAND-flash IO1 / General-purpose IO Port 0, bit 1.
4 NFDIO2/GPIO0_2 bidirectional NAND-flash IO2 / General-purpose IO Port 0, bit 2.
5 NFDIO3/GPIO0_3 bidirectional NAND-flash IO3 / General-purpose IO Port 0, bit 3.
6 DGND0 power_in Core & I/O ground.
7 IOVDD1 power_in I/O power supply.
8 TEST input Test mode input (active high), must be connected to DGND.
9 NFDIO4/GPIO0_4 bidirectional NAND-flash IO4 / General-purpose IO Port 0, bit 4.
10 NFDIO5/GPIO0_5 bidirectional NAND-flash IO5 / General-purpose IO Port 0, bit 5.
11 NFDIO6/GPIO0_6 bidirectional NAND-flash IO6 / General-purpose IO Port 0, bit 6.
12 NFDIO7/GPIO0_7 bidirectional NAND-flash IO7 / General-purpose IO Port 0, bit 7.
13 NFRDY/GPIO0_8 bidirectional NAND-flash READY / General-purpose IO Port 0, bit 8.
14 NFRD/GPIO0_9 bidirectional NAND-flash RD / General-purpose IO Port 0, bit 9.
15 NFCE/GPIO0_10 bidirectional NAND-flash CE / General-purpose IO Port 0, bit 10.
16 NFCLE/GPIO0_12 bidirectional NAND-flash CLE / General-purpose IO Port 0, bit 12.
17 NFALE/GPIO0_13 bidirectional NAND-flash ALE / General-purpose IO Port 0, bit 13.
18 DGND1 power_in Core & I/O ground.
19 IOVDD2 power_in I/O power supply.
20 NFWR/GPIO0_11 bidirectional NAND-flash WR / General-purpose IO Port 0, bit 11.
21 CS2/GPIO0_14 bidirectional General-purpose IO Port 0, bit 14.
22 XCS/GPIO1_0 bidirectional SPI XCS / General-Purpose I/O Port 1, bit 0.
23 SCLK/GPIO1_1 bidirectional SPI CLK / General-Purpose I/O Port 1, bit 1.
24 SI/GPIO1_2 bidirectional SPI MISO / General-Purpose I/O Port 1, bit 2.
25 SO/GPIO1_3 bidirectional SPI MOSI / General-Purpose I/O Port 1, bit 3.
26 TX/GPIO1_4 bidirectional UART TX / General-Purpose I/O Port 1, bit 4.
27 RX/GPIO1_5 bidirectional UART RX / General-Purpose I/O Port 1, bit 5.
28 XTALI input Crystal input, must be 12 MHz for USB operation.
29 XTALO output Crystal output.
30 IOVDD power_in I/O power supply, Regulator output; must be connected to IOVDD1 and IOVDD2 input pins.
31 DGND2 power_in Core & I/O ground.
32 CVDD power_in Core power supply, Regulator output with recommended range 1.8 to 2.6 V.
33 VHIGH power_in Power supply, Regulator input with recommended range 4.0 to 5.25 V.
34 AVDD power_in Analog power supply, Regulator output with recommended range 2.75 to 3.6 V; must be connected to AVDD1, AVDD2, and AVDD3 pins.
35 USBP bidirectional USB differential + in / out with controllable 1.5 kΩ pull-up.
36 USBN bidirectional USB differential - in / out.
37 PWRBTN input Power button for Regulator startup and Power Key input; voltage must not exceed 3.6 V.
38 AGND0 power_in Analog ground.
39 AVDD1 power_in Analog power supply; must have proper bypass capacitors.
40 RIGHT output Right channel audio output with full-scale voltage 450 to 600 mVrms.
41 AGND1 power_in Analog ground.
42 AGND2 power_in Analog ground.
43 CBUF output Common voltage buffer for headphones with 1.2 V nominal level and 130 to 200 mA disconnect current (short-circuit protection).
44 AVDD2 power_in Analog power supply; must have proper bypass capacitors.
45 RCAP bidirectional Filtering capacitance for reference.
46 AVDD3 power_in Analog power supply; must have proper bypass capacitors.
47 LEFT output Left channel audio output with full-scale voltage 450 to 600 mVrms.
48 AGND3 power_in Analog ground.

Key specifications

Parameter Value
Manufacturer VLSI Solution
Package LQFP-48(7x7)
Category Interface
Pins 48

CAD (KiCad official)

  • Symbol: VS1000D-L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: vs1000d-l-etched.step / vs1000d-l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vs1000d-l.step / vs1000d-l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VLSI Solution datasheet (29 pp, sha256 fe573d059c3e622a, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF