component
VRD1828MTX
Public Made by Adomby adom
AnaSem Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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VRD1828MTX
AnaSem · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-6
VRD1828MTX from AnaSem, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN1 | input | Enable input for channel 1; driving it to VSS shuts down VOUT1 and discharges CL through the internal auto-discharge resistance (160 Ω typ.), with EN high level specified at 1.2 V to 6.0 V and EN low level at 0 to 0.3 V. |
| 2 | VIN | power_in | Common voltage input for both regulators, specified at 1.6 V to 6.0 V with an absolute maximum range of −0.3 V to +7.0 V, and a 1 µF input capacitor is recommended between VIN and VSS. |
| 3 | EN2 | input | Enable input for channel 2; driving it to VSS shuts down VOUT2 and discharges CL through the internal auto-discharge resistance (160 Ω typ.), with EN high level specified at 1.2 V to 6.0 V and EN low level at 0 to 0.3 V. |
| 4 | VOUT2 | power_out | Channel 2 regulated output, which must not exceed VIN + 0.3 V to avoid reverse current through the parasitic diode, and a at least 1.0 µF ceramic output capacitor should be connected close to this pin and VSS. |
| 5 | VSS | power_in | Power ground and common return for both regulators and the output capacitors. |
| 6 | VOUT1 | power_out | Channel 1 regulated output, which must not exceed VIN + 0.3 V to avoid reverse current through the parasitic diode, and a at least 1.0 µF ceramic output capacitor should be connected close to this pin and VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AnaSem |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy, Ch-1 (VOUT1 = 1.80V) | VOUT | -20 | 20 | mV | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA, Ta=-40°C ~ +85°C; VOUT≦1.90V | 7 | |
| Output voltage accuracy, Ch-2 (VOUT2 = 2.80V) | VOUT | -1 | 1 | % | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA, Ta=-40°C ~ +85°C; VOUT≧1.95V (printed ±1%) | 7 | |
| Dropout voltage, Ch-1 (VOUT1 = 1.80V) | VDROP | 130 | 205 | mV | IOUT=100mA; 1.7V≦VOUT≦2.25V | 7 | |
| Dropout voltage, Ch-2 (VOUT2 = 2.80V) | VDROP | 100 | 150 | mV | IOUT=100mA; 2.3V≦VOUT≦2.85V | 7 | |
| Current consumption | IDD | 50 | 80 | µA | VIN=VOUT+1.0V, VOUT=Open, IOUT=0mA | 8 | |
| Standby current | ISTB | 0.01 | 0.1 | µA | EN=VSS | 8 | |
| Input voltage | VIN | 1.6 | 6 | V | 8 | ||
| Load regulation | ∆VOUT | 10 | 40 | mV | VIN=VOUT+1.0V, IOUT=0.1mA ~100mA | 8 | |
| Line regulation | ∆VOUT / ∆VIN•VOUT | 0.01 | 0.1 | %/V | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA | 8 | |
| Limit current | ILIMIT | 300 | mA | EN=VIN | 8 | ||
| Output voltage temperature coefficient | ∆VOUT / ∆Ta•VOUT | -20 | 20 | ppm/°C | VEN=VIN, IOUT=300mA, Ta=-40°C ~ +85°C | 8 | |
| EN high level voltage | VENH | 1.2 | 6 | V | 8 | ||
| EN low level voltage | VENL | 0.3 | V | 8 | |||
| EN high level current | IENH | -0.1 | 0.1 | µA | VEN= VIN | 8 | |
| EN low level current | IENL | -0.1 | 0.1 | µA | VEN= VSS | 8 | |
| Input voltage range (absolute maximum) | VIN | -0.3 | 7 | V | 6 | ||
| Output current (absolute maximum) | IOUT | 500 | mA | 6 | |||
| Output voltage range (absolute maximum) | VOUT | -0.3 | V | Min is VSS-0.3 V and max is VIN+0.3 V (both relative to VSS/VIN; no fixed max printed) | 6 | ||
| Power dissipation (absolute maximum) | PD | 600 | mW | SOT-26; PCB 50mm×50mm×1.6mm (note ※1) | 6 | ||
| Operating temperature range | TOPR | -40 | 85 | °C | 6 | ||
| Storage temperature range | TSTG | -55 | 125 | °C | 6 |
CAD (KiCad official)
- Symbol:
VRD1828MTX - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
vrd1828mtx-etched.step/vrd1828mtx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vrd1828mtx.step/vrd1828mtx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: AnaSem datasheet (35 pp, sha256
7f8a0b5646548c27, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# VRD1828MTX
**AnaSem** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-6
VRD1828MTX from AnaSem, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN1 | input | Enable input for channel 1; driving it to VSS shuts down VOUT1 and discharges CL through the internal auto-discharge resistance (160 Ω typ.), with EN high level specified at 1.2 V to 6.0 V and EN low level at 0 to 0.3 V. |
| 2 | VIN | power_in | Common voltage input for both regulators, specified at 1.6 V to 6.0 V with an absolute maximum range of −0.3 V to +7.0 V, and a 1 µF input capacitor is recommended between VIN and VSS. |
| 3 | EN2 | input | Enable input for channel 2; driving it to VSS shuts down VOUT2 and discharges CL through the internal auto-discharge resistance (160 Ω typ.), with EN high level specified at 1.2 V to 6.0 V and EN low level at 0 to 0.3 V. |
| 4 | VOUT2 | power_out | Channel 2 regulated output, which must not exceed VIN + 0.3 V to avoid reverse current through the parasitic diode, and a at least 1.0 µF ceramic output capacitor should be connected close to this pin and VSS. |
| 5 | VSS | power_in | Power ground and common return for both regulators and the output capacitors. |
| 6 | VOUT1 | power_out | Channel 1 regulated output, which must not exceed VIN + 0.3 V to avoid reverse current through the parasitic diode, and a at least 1.0 µF ceramic output capacitor should be connected close to this pin and VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | AnaSem |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage accuracy, Ch-1 (VOUT1 = 1.80V) | VOUT | -20 | | 20 | mV | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA, Ta=-40°C ~ +85°C; VOUT≦1.90V | 7 |
| Output voltage accuracy, Ch-2 (VOUT2 = 2.80V) | VOUT | -1 | | 1 | % | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA, Ta=-40°C ~ +85°C; VOUT≧1.95V (printed ±1%) | 7 |
| Dropout voltage, Ch-1 (VOUT1 = 1.80V) | VDROP | | 130 | 205 | mV | IOUT=100mA; 1.7V≦VOUT≦2.25V | 7 |
| Dropout voltage, Ch-2 (VOUT2 = 2.80V) | VDROP | | 100 | 150 | mV | IOUT=100mA; 2.3V≦VOUT≦2.85V | 7 |
| Current consumption | IDD | | 50 | 80 | µA | VIN=VOUT+1.0V, VOUT=Open, IOUT=0mA | 8 |
| Standby current | ISTB | | 0.01 | 0.1 | µA | EN=VSS | 8 |
| Input voltage | VIN | 1.6 | | 6 | V | | 8 |
| Load regulation | ∆VOUT | | 10 | 40 | mV | VIN=VOUT+1.0V, IOUT=0.1mA ~100mA | 8 |
| Line regulation | ∆VOUT / ∆VIN•VOUT | | 0.01 | 0.1 | %/V | VOUT+1.0V≦VIN≦6.0V, IOUT=30mA | 8 |
| Limit current | ILIMIT | 300 | | | mA | EN=VIN | 8 |
| Output voltage temperature coefficient | ∆VOUT / ∆Ta•VOUT | -20 | | 20 | ppm/°C | VEN=VIN, IOUT=300mA, Ta=-40°C ~ +85°C | 8 |
| EN high level voltage | VENH | 1.2 | | 6 | V | | 8 |
| EN low level voltage | VENL | | | 0.3 | V | | 8 |
| EN high level current | IENH | -0.1 | | 0.1 | µA | VEN= VIN | 8 |
| EN low level current | IENL | -0.1 | | 0.1 | µA | VEN= VSS | 8 |
| Input voltage range (absolute maximum) | VIN | -0.3 | | 7 | V | | 6 |
| Output current (absolute maximum) | IOUT | | | 500 | mA | | 6 |
| Output voltage range (absolute maximum) | VOUT | -0.3 | | | V | Min is VSS-0.3 V and max is VIN+0.3 V (both relative to VSS/VIN; no fixed max printed) | 6 |
| Power dissipation (absolute maximum) | PD | | | 600 | mW | SOT-26; PCB 50mm×50mm×1.6mm (note ※1) | 6 |
| Operating temperature range | TOPR | -40 | | 85 | °C | | 6 |
| Storage temperature range | TSTG | -55 | | 125 | °C | | 6 |
## CAD (KiCad official)
- Symbol: `VRD1828MTX`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `vrd1828mtx-etched.step` / `vrd1828mtx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vrd1828mtx.step` / `vrd1828mtx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [AnaSem datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588918358775640064) (35 pp, sha256 `7f8a0b5646548c27`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/vrd1828mtx-datasheet.pdf)