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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	vps8703b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	vps8703b: viewers · Ray	1mo ago
package.json	vps8703b: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
page.json	vps8703b: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray	1mo ago
README.md	vps8703b: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago
vps8703b-etched.fit.json	vps8703b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
vps8703b-etched.glb	vps8703b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
vps8703b-etched.step	vps8703b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
vps8703b.glb	Publish 0.1.0 · Ray	1mo ago
vps8703b.kicad_mod	Publish 0.1.0 · Ray	1mo ago
vps8703b.kicad_sym	Publish 0.1.0 · Ray	1mo ago
vps8703b.lbr	Publish 0.1.0 · Ray	1mo ago
vps8703b.step	Publish 0.1.0 · Ray	1mo ago

VPS8703B

VPSC · Power Management - Specialized · ESOP8

VPS8703B from VPSC, in a ESOP8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLK	input	External clock input and dead-zone time adaptive mode selection; when floating, internal pull-up selects 250 kHz fixed dead-zone; when tied to GND, enables adaptive dead-zone mode; accepts external clock for synchronization.
2	GND	power_in	Ground reference for logic and analog circuits.
3	VIN	power_in	Power supply input, 6-30V nominal; bypass with 1 µF ceramic capacitor placed adjacent to device pins.
4	EN	input	Active-high logic enable; pulling to low stops chip operation and enables ultra-low standby mode (~19 µA); floating defaults to high via internal pull-up.
5	VD2	output	Bridge leg 2 transformer drive output (complementary to VD1); peak drain current 1.6 A absolute maximum, rated for VIN+0.3 V.
6	NC	unconnected	No internal connection; may be left unconnected or tied to ground.
7	NC	unconnected	No internal connection; may be left unconnected or tied to ground.
8	VD1	output	Bridge leg 1 transformer drive output (complementary to VD2); peak drain current 1.6 A absolute maximum, rated for VIN+0.3 V.
9	EP	power_in	Exposed thermal pad internally bonded to GND; not used as primary electrical connection but must be soldered to large ground plane to enhance heat dissipation.

Key specifications

Parameter	Value
Manufacturer	VPSC
Package	ESOP8
Category	Power Management (PMIC)
Pins	9

CAD (KiCad official)

Symbol: VPS8703B
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
3D model: ESOP8 (KiCad packages3D, STEP)
3D model files: vps8703b-etched.step / vps8703b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vps8703b.step / vps8703b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: VPSC datasheet (12 pp, sha256 7e0212bdecfb48f8, retrieved 2026-09-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF