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VPS8701B

Public Made by Adom

by adom

VPSC DC-DC Converters, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs Publish 0.1.0 · Ray 1mo ago
viewers vps8701b: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json vps8701b: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 26d ago
README.md vps8701b: specified limits as data (metadata.characteristics, 36 rows from the datasheet) · Ray 26d ago
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vps8701b-etched.step vps8701b: factory component page (tier=lcsc) · Ray 1mo ago
vps8701b-hero.glb vps8701b: hero GLB from the etched model (keeps the MPN mark) · Ray 1mo ago
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VPS8701B

VPSC · DC-DC Converters · SOT-23-6

VPS8701B from VPSC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable pin: pulling it low stops the chip, while leaving it floating or high lets the chip run normally.
2 GND power_in Common ground for the logic circuits and the analog circuits.
3 CLK input Internal clock frequency select and external clock input: floating gives a typical 250 kHz internal frequency, tying to GND gives 350 kHz, and an applied external clock produces complementary drive at half its frequency (external clock range 50 to 1600 kHz).
4 VD2 output Transformer drive output 2 (drain of the internal power MOSFET bridge leg; absolute maximum VIN+0.3 V).
5 VIN power_in Power input, recommended 6 to 30 V (absolute maximum 38 V); bypass to GND with a 1 µF capacitor placed as close to the device as possible.
6 VD1 output Transformer drive output 1 (drain of the internal power MOSFET bridge leg; absolute maximum VIN+0.3 V).

Key specifications

Parameter Value
Manufacturer VPSC
Package SOT-23-6
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN input voltage (absolute maximum) VIN -0.3 38 V 2
LDMOS drain voltage VD1, VD2 VD1, VD2 -0.3 V 2
LDMOS peak current I(VD1)Pk, I(VD2)Pk 1.2 A 2
EN, CLK pin voltage EN, CLK -0.3 6.6 V 2
Maximum operating junction temperature TJMAX 150 ℃ 2
Storage temperature range TSTG -55 150 ℃ 2
ESD human body model HBM V(ESD) -2000 2000 V HBM per ESDA/JEDEC JS-001-2017 2
ESD charged device model CDM V(ESD) -1000 1000 V CDM per ESDA/JEDEC JS-002-2014 2
Input voltage range (recommended) VIN 6 30 V 3
LDMOS drain current (recommended) IVD1, IVD2 0.3 A 3
Operating junction temperature TJ -40 125 ℃ 3
VIN input voltage range VIN 6 30 V 3
Startup voltage VIN(ON) 4.3 4.8 6 V EN floating, VIN rising 3
VIN quiescent current IQ 1.5 2.1 2.8 mA VD1, VD2, CLK, EN floating 3
VIN current with enable off IVIN(EN) 19 30 uA EN=0 3
EN turn-on voltage VEN(ON) 2.1 2.5 V VEN rising 3
EN turn-off hysteresis voltage VEN(HYS) 0.7 1 1.3 V VEN falling 3
EN source current IEN(SRC) 13 40 uA VEN rising to VEN(ON)+0.1V 3
Current clamp limit initial value ILIM0 180 250 350 mA VD1 and VD2 shorted, VIN=6V; measure IVIN current 3
Current clamp limit steady-state value ILIM1 350 450 600 mA 3
Low-frequency internal clock fSW0 225 250 275 kHz CLK floating 3
High-frequency internal clock fSW1 315 350 385 kHz CLK connected to GND 3
CLK high-level logic voltage VCLK(H) 2.2 2.5 V 3
CLK low-level logic voltage VCLK(L) 0.7 1.2 V 3
External synchronization clock frequency F(EXT) 50 1600 kHz 3
Over-temperature protection threshold TSHDN 145 162 178 ℃ 3
Over-temperature protection minimum off time TOFFMIN(OTP) 2 18 Tsw 3
VIN enable-off hysteresis voltage VIN(HYS) 0.3 V EN floating, VIN falling 3
NMOS on-resistance at 25 °C RDSN(ON) 0.25 Ω T=25℃, IDS=0.2A 3
NMOS on-resistance at 100 °C RDSN(ON) 0.34 Ω T=100℃, IDS=0.2A 3
PMOS on-resistance at 25 °C RDSP(ON) 0.6 Ω T=25℃, IDS=0.2A 3
PMOS on-resistance at 100 °C RDSP(ON) 0.8 Ω T=100℃, IDS=0.2A 3
Voltage slew rate VSLEW 350 V/us 240Ω resistor between VD1 and VD2 3
Dead time between VD1 and VD2 tBBM 180 ns 240Ω resistor between VD1 and VD2 3
Time for ILIM0 to rise to ILIM1 tSS 1 mS 3
Over-temperature protection hysteresis TSHDN(HYS) 27 ℃ 3

CAD (KiCad official)

  • Symbol: VPS8701B
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: vps8701b-etched.step / vps8701b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vps8701b.step / vps8701b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VPSC datasheet (14 pp, sha256 2cde9e84335b29f2, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF