component
VPC28C44
Public Made by Adomby adom
VPSC DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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VPC28C44
VPSC · DC-DC Converters · SOP-8
VPC28C44 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Error amplifier compensation pin where the external compensation network connects; the amplifier is internally current-limited, so forcing COMP to ground sets zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier (non-inverting input is internally fixed at 2.5 V), used for the voltage feedback loop, with the lead kept short for stability. |
| 3 | CS | input | Primary-side current sense input tied to the sense resistor that terminates OUT conduction via the PWM comparator, with a typical maximum comparison threshold of 1 V. |
| 4 | RT/CT | passive | Oscillator timing pin: timing resistor RT connects from VREF and timing capacitor CT to GND, with f_OSC ≈ 1.6/(RT×CT) and RT never to be below 5 kΩ. |
| 5 | GND | power_in | Analog ground and signal/power return for packages without a separate PGND pin, which should be kept separate from the high-current gate-drive return path. |
| 6 | OUT | output | Push-pull gate drive output for directly driving an external MOSFET, sourcing and sinking up to 1 A peak, and held low when VDD is below the turn-on threshold; absolute maximum voltage to GND is 30 V. |
| 7 | VDD | power_in | Controller bias supply input, with absolute maximum 30 V and recommended maximum 28 V, requiring a ~0.1 µF bypass capacitor close to the pin and an additional bulk capacitor at least 10× the main switch gate capacitance. |
| 8 | VREF | power_out | 5 V reference output derived from VDD, which requires a minimum 0.1 µF ceramic bypass capacitor placed as close to the pin as possible and additional bypass for any external load. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VPSC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD | VDD | 30 | V | 2 | |||
| Input current VDD | VDD | 30 | mA | 2 | |||
| Output peak current | -1 | 1 | A | 2 | |||
| Analog pins (COMP, CS, FB, RT/CT) to GND | -0.3 | 6 | V | 2 | |||
| Reference voltage (VREF) to GND | VREF | 6.6 | V | 2 | |||
| Output pin (OUT) to GND | OUT | -0.3 | 30 | V | 2 | ||
| Error amplifier output sink current | 15 | mA | 2 | ||||
| Maximum operating junction temperature | TJMAX | 150 | ℃ | 2 | |||
| ESD HBM | V(ESD) | -3000 | 3000 | V | per ESDA/JEDEC JS-001-2017; Zap 1 pulse, interval >=0.1S | 3 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | per ESDA/JEDEC JS-002-2014 | 3 | |
| Input voltage | VVDD | 28 | V | 3 | |||
| FB reference voltage | VFB | 2.5 | V | 3 | |||
| Current sense input voltage | VCS | 1 | V | 3 | |||
| Supply current | IVDD | 25 | mA | 3 | |||
| Average output current | IOUT | 200 | mA | 3 | |||
| Reference output source current | IVREF | -20 | mA | 3 | |||
| Oscillator frequency | fOSC | 1 | MHz | 3 | |||
| Operating temperature (VPC28C4x) | -40 | 105 | ℃ | VPC28C4x | 3 | ||
| VREF reference voltage | VREF | 4.9 | 5 | 5.1 | V | IVREF = 1 mA, TJ = 25°C | 4 |
| VREF line regulation | ∆VREF | 2 | 20 | mV | 12≤VDD≤25V | 4 | |
| VREF load regulation | ∆VREF | 3 | 25 | mV | 1mA≤IVREF≤20mA | 4 | |
| VREF temperature coefficient | ∆VREF/∆T | 0.2 | 0.4 | mV/℃ | 4 | ||
| VREF total output variation | 4.82 | 5.18 | V | 线性、负载、温度 | 4 | ||
| VREF long-term stability | 5 | 25 | mV | 1000 小时，TA= 125°C | 4 | ||
| VREF short-circuit current | ISC | -30 | -50 | -70 | mA | 4 | |
| Oscillator frequency (set 1) | fOSC | 49 | 52 | 55 | kHz | TA=25℃，RT=10kΩ，CT=3.3nF | 4 |
| Oscillator frequency (set 2) | fOSC | 225 | 250 | 275 | kHz | TA=25℃，RT=6.2kΩ，CT=1.0nF | 4 |
| Oscillator frequency variation with voltage | ∆fOSC/∆V | 0.2 | 1 | % | 12V≤VDD≤25V | 4 | |
| Oscillator frequency variation with temperature | ∆fOSC/∆T | 1 | 2.5 | % | -40℃≤TA≤125℃ | 4 | |
| RT/CT discharge current at 25°C | Idischarge | 7.8 | 8.3 | 8.8 | mA | TJ = 25°C | 4 |
| RT/CT discharge current over temperature | Idischarge | 7.6 | 9 | mA | -40℃≤TA≤125℃ | 4 | |
| FB reference voltage | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP=2.5V, TA=25℃ | 4 |
| FB input bias current | IFB | -1 | -0.1 | uA | VFB=5V | 4 | |
| Error amplifier open-loop gain | AVOL | 70 | 95 | dB | 2V≤VO≤4V | 4 | |
| Error amplifier unity-gain bandwidth | BW | 0.7 | 1 | MHz | TJ = 25°C | 4 | |
| Error amplifier PSRR | PSRR | 60 | 70 | dB | 12V≤VDD≤25V | 4 | |
| COMP sink current | ICOMP(SNK) | 2 | 10 | mA | VFB=2.7V，VFB=1.1V | 4 | |
| COMP source current | ICOMP(SRC) | -1 | -0.5 | mA | VFB=2.3V，VFB=5V | 4 | |
| VOUT high level (COMP) | VOH | 5.4 | 6 | 6.6 | V | VFB=2.3V，RCOMP=15kΩ到地 | 4 |
| VOUT low level (COMP) | VOL | 0.1 | 0.5 | V | VFB=2.7V，RCOMP=15kΩ到 8 脚 | 4 | |
| Current sense gain | ACS | 2.85 | 3 | 3.15 | V/V | 4 | |
| Maximum comparator threshold voltage | VCS_th | 0.9 | 1 | 1.1 | V | VFB＜2.4V | 4 |
| CS input bias current | ICS | -2 | -0.1 | uA | 4 | ||
| Delay from CS to OUT | tD | 30 | 65 | nS | VCS jumps from 0 to 2V | 4 | |
| OUT on-resistance, low state | RDSON(OL) | 4 | 10 | Ω | ISINK=200mA | 4 | |
| OUT on-resistance, high state | RDSON(OH) | 8 | 16 | Ω | ISOURCE=200mA | 4 | |
| OUT pull-down current during UVLO | IOUT(SNK) | 100 | 300 | mA | VDD=6V，VOUT=1V | 4 | |
| OUT rise time | tr | 30 | 55 | nS | TJ=25℃，CL=1nF | 4 | |
| OUT fall time | tf | 20 | 40 | nS | TJ=25℃，CL=1nF | 4 | |
| Start-up threshold voltage VDD(ON) (VPCx8C42/VPCx8C44) | VDD(ON) | 13.6 | 14.6 | 15.6 | V | VPCx8C42/VPCx8C44 | 5 |
| UVLO threshold voltage VDD(OFF) (VPCx8C42/VPCx8C44) | VDD(OFF) | 7.7 | 8.7 | 9.7 | V | VPCx8C42/VPCx8C44 | 5 |
| Maximum duty cycle (VPCx8C44 family) | DMAX | 47 | 48 | 50 | % | VPCx8C44/VPCx8C45/VPCx8C41, VFB＜2.4V | 5 |
| Minimum duty cycle | DMIN | 0 | 0 | % | VFB＞2.6V | 5 | |
| Start-up current | IST | 50 | 100 | uA | VDD= VDD(ON)-0.5V | 5 | |
| Quiescent operating current (VDD(ON)+0.5V) | IVDD | 2.7 | 3.5 | mA | VFB=VCS=0V，VDD=VDD(ON)+0.5V | 5 | |
| Quiescent operating current (VDD=25V) | IVDD | 8 | 14 | 17 | mA | VFB=VCS=0V，VDD=25V | 5 |
| VDD clamp voltage | VDD(clamp) | 30 | 34 | V | IVDD=25mA | 5 |
CAD (KiCad official)
- Symbol:
VPC28C44 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
vpc28c44-etched.step/vpc28c44-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vpc28c44.step/vpc28c44.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VPSC datasheet (15 pp, sha256
41de8f28b106ea3c, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# VPC28C44
**VPSC** · DC-DC Converters · SOP-8
VPC28C44 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Error amplifier compensation pin where the external compensation network connects; the amplifier is internally current-limited, so forcing COMP to ground sets zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier (non-inverting input is internally fixed at 2.5 V), used for the voltage feedback loop, with the lead kept short for stability. |
| 3 | CS | input | Primary-side current sense input tied to the sense resistor that terminates OUT conduction via the PWM comparator, with a typical maximum comparison threshold of 1 V. |
| 4 | RT/CT | passive | Oscillator timing pin: timing resistor RT connects from VREF and timing capacitor CT to GND, with f_OSC ≈ 1.6/(RT×CT) and RT never to be below 5 kΩ. |
| 5 | GND | power_in | Analog ground and signal/power return for packages without a separate PGND pin, which should be kept separate from the high-current gate-drive return path. |
| 6 | OUT | output | Push-pull gate drive output for directly driving an external MOSFET, sourcing and sinking up to 1 A peak, and held low when VDD is below the turn-on threshold; absolute maximum voltage to GND is 30 V. |
| 7 | VDD | power_in | Controller bias supply input, with absolute maximum 30 V and recommended maximum 28 V, requiring a ~0.1 µF bypass capacitor close to the pin and an additional bulk capacitor at least 10× the main switch gate capacitance. |
| 8 | VREF | power_out | 5 V reference output derived from VDD, which requires a minimum 0.1 µF ceramic bypass capacitor placed as close to the pin as possible and additional bypass for any external load. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VPSC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VDD | VDD | | | 30 | V | | 2 |
| Input current VDD | VDD | | | 30 | mA | | 2 |
| Output peak current | | -1 | | 1 | A | | 2 |
| Analog pins (COMP, CS, FB, RT/CT) to GND | | -0.3 | | 6 | V | | 2 |
| Reference voltage (VREF) to GND | VREF | | | 6.6 | V | | 2 |
| Output pin (OUT) to GND | OUT | -0.3 | | 30 | V | | 2 |
| Error amplifier output sink current | | | | 15 | mA | | 2 |
| Maximum operating junction temperature | TJMAX | | | 150 | ℃ | | 2 |
| ESD HBM | V(ESD) | -3000 | | 3000 | V | per ESDA/JEDEC JS-001-2017; Zap 1 pulse, interval >=0.1S | 3 |
| ESD CDM | V(ESD) | -1000 | | 1000 | V | per ESDA/JEDEC JS-002-2014 | 3 |
| Input voltage | VVDD | | | 28 | V | | 3 |
| FB reference voltage | VFB | | 2.5 | | V | | 3 |
| Current sense input voltage | VCS | | 1 | | V | | 3 |
| Supply current | IVDD | | | 25 | mA | | 3 |
| Average output current | IOUT | | | 200 | mA | | 3 |
| Reference output source current | IVREF | -20 | | | mA | | 3 |
| Oscillator frequency | fOSC | | | 1 | MHz | | 3 |
| Operating temperature (VPC28C4x) | | -40 | | 105 | ℃ | VPC28C4x | 3 |
| VREF reference voltage | VREF | 4.9 | 5 | 5.1 | V | IVREF = 1 mA, TJ = 25°C | 4 |
| VREF line regulation | ∆VREF | 2 | | 20 | mV | 12≤VDD≤25V | 4 |
| VREF load regulation | ∆VREF | 3 | | 25 | mV | 1mA≤IVREF≤20mA | 4 |
| VREF temperature coefficient | ∆VREF/∆T | 0.2 | | 0.4 | mV/℃ | | 4 |
| VREF total output variation | | 4.82 | | 5.18 | V | 线性、负载、温度 | 4 |
| VREF long-term stability | | 5 | | 25 | mV | 1000 小时，TA= 125°C | 4 |
| VREF short-circuit current | ISC | -30 | -50 | -70 | mA | | 4 |
| Oscillator frequency (set 1) | fOSC | 49 | 52 | 55 | kHz | TA=25℃，RT=10kΩ，CT=3.3nF | 4 |
| Oscillator frequency (set 2) | fOSC | 225 | 250 | 275 | kHz | TA=25℃，RT=6.2kΩ，CT=1.0nF | 4 |
| Oscillator frequency variation with voltage | ∆fOSC/∆V | 0.2 | | 1 | % | 12V≤VDD≤25V | 4 |
| Oscillator frequency variation with temperature | ∆fOSC/∆T | 1 | | 2.5 | % | -40℃≤TA≤125℃ | 4 |
| RT/CT discharge current at 25°C | Idischarge | 7.8 | 8.3 | 8.8 | mA | TJ = 25°C | 4 |
| RT/CT discharge current over temperature | Idischarge | 7.6 | | 9 | mA | -40℃≤TA≤125℃ | 4 |
| FB reference voltage | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP=2.5V, TA=25℃ | 4 |
| FB input bias current | IFB | -1 | | -0.1 | uA | VFB=5V | 4 |
| Error amplifier open-loop gain | AVOL | 70 | | 95 | dB | 2V≤VO≤4V | 4 |
| Error amplifier unity-gain bandwidth | BW | 0.7 | | 1 | MHz | TJ = 25°C | 4 |
| Error amplifier PSRR | PSRR | 60 | | 70 | dB | 12V≤VDD≤25V | 4 |
| COMP sink current | ICOMP(SNK) | 2 | | 10 | mA | VFB=2.7V，VFB=1.1V | 4 |
| COMP source current | ICOMP(SRC) | -1 | | -0.5 | mA | VFB=2.3V，VFB=5V | 4 |
| VOUT high level (COMP) | VOH | 5.4 | 6 | 6.6 | V | VFB=2.3V，RCOMP=15kΩ到地 | 4 |
| VOUT low level (COMP) | VOL | 0.1 | | 0.5 | V | VFB=2.7V，RCOMP=15kΩ到 8 脚 | 4 |
| Current sense gain | ACS | 2.85 | 3 | 3.15 | V/V | | 4 |
| Maximum comparator threshold voltage | VCS_th | 0.9 | 1 | 1.1 | V | VFB＜2.4V | 4 |
| CS input bias current | ICS | -2 | | -0.1 | uA | | 4 |
| Delay from CS to OUT | tD | 30 | | 65 | nS | VCS jumps from 0 to 2V | 4 |
| OUT on-resistance, low state | RDSON(OL) | 4 | | 10 | Ω | ISINK=200mA | 4 |
| OUT on-resistance, high state | RDSON(OH) | 8 | | 16 | Ω | ISOURCE=200mA | 4 |
| OUT pull-down current during UVLO | IOUT(SNK) | 100 | | 300 | mA | VDD=6V，VOUT=1V | 4 |
| OUT rise time | tr | 30 | | 55 | nS | TJ=25℃，CL=1nF | 4 |
| OUT fall time | tf | 20 | | 40 | nS | TJ=25℃，CL=1nF | 4 |
| Start-up threshold voltage VDD(ON) (VPCx8C42/VPCx8C44) | VDD(ON) | 13.6 | 14.6 | 15.6 | V | VPCx8C42/VPCx8C44 | 5 |
| UVLO threshold voltage VDD(OFF) (VPCx8C42/VPCx8C44) | VDD(OFF) | 7.7 | 8.7 | 9.7 | V | VPCx8C42/VPCx8C44 | 5 |
| Maximum duty cycle (VPCx8C44 family) | DMAX | 47 | 48 | 50 | % | VPCx8C44/VPCx8C45/VPCx8C41, VFB＜2.4V | 5 |
| Minimum duty cycle | DMIN | 0 | | 0 | % | VFB＞2.6V | 5 |
| Start-up current | IST | 50 | | 100 | uA | VDD= VDD(ON)-0.5V | 5 |
| Quiescent operating current (VDD(ON)+0.5V) | IVDD | 2.7 | | 3.5 | mA | VFB=VCS=0V，VDD=VDD(ON)+0.5V | 5 |
| Quiescent operating current (VDD=25V) | IVDD | 8 | 14 | 17 | mA | VFB=VCS=0V，VDD=25V | 5 |
| VDD clamp voltage | VDD(clamp) | 30 | | 34 | V | IVDD=25mA | 5 |
## CAD (KiCad official)
- Symbol: `VPC28C44`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `vpc28c44-etched.step` / `vpc28c44-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vpc28c44.step` / `vpc28c44.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VPSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590907009024155648) (15 pp, sha256 `41de8f28b106ea3c`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/vpc28c44-datasheet.pdf)