component
VPC2845
Public Made by Adomby adom
VPSC DC-DC Converters, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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VPC2845
VPSC · DC-DC Converters · SOP-8
VPC2845 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin: external compensation components connect here to shape the error amplifier output, and the amplifier is internally current-limited so forcing COMP to GND gives zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, where the FB lead should be kept short and stray capacitance minimized for stability. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical comparator threshold VCS_th of 1 V and an optional voltage ramp for voltage-mode operation. |
| 4 | RT/CT | passive | Oscillator timing pin: timing resistor RT connects from VREF and timing capacitor CT connects to GND, giving fOSC = 1.6/(RT x CT), and RT must not be less than 5 kΩ. |
| 5 | GND | power_in | Analog and signal ground, which also serves as power ground on packages without a separate PGND; keep the signal return path separate from the high-current gate-driver return path. |
| 6 | OUT | output | Push-pull gate drive output for the external MOSFET that sources and sinks up to 1 A peak and is held low while VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Controller bias supply input, which should stay below the 28 V maximum recommended operating voltage (30 V absolute maximum) and be bypassed with a typical 0.1 µF capacitor placed directly at the pin. |
| 8 | VREF | power_out | 5 V reference output that requires a minimum 0.1 µF ceramic bypass capacitor placed as close to the pin as possible, with an additional bypass capacitor needed if other external loads are connected. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VPSC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 VDD (absolute maximum) | VDD | 30 | V | 3 | |||
| 输入电流 VDD | VDD | 30 | mA | 3 | |||
| 输出峰值电流 | OUT | -1 | 1 | A | 3 | ||
| 模拟引脚对 GND (COMP、CS、FB、RT/CT) | COMP, CS, FB, RT/CT | -0.3 | 6 | V | 3 | ||
| 基准电压对 GND | VREF | 6.6 | V | 3 | |||
| 输出引脚对 GND | OUT | -0.3 | 30 | V | 3 | ||
| 误差放大器输出吸入电流 | COMP | 15 | mA | 3 | |||
| 最大工作结温 | TJMAX | 150 | ℃ | 3 | |||
| ESD 人体模式 HBM | V(ESD) | -3000 | 3000 | V | per ESDA/JEDEC JS-001-2017 | 3 | |
| ESD 机器模式 CDM | V(ESD) | -1000 | 1000 | V | per ESDA/JEDEC JS-002-2014 | 3 | |
| 输入电压 VDD (recommended) | VVDD | 28 | V | 3 | |||
| FB 基准电压 | VFB | 2.5 | V | 3 | |||
| 电流采样输入 | VCS | 1 | V | 3 | |||
| 电源电流 | IVDD | 25 | mA | 3 | |||
| 输出平均电流 | IOUT | 200 | mA | 3 | |||
| 基准电源输出电流 | IVREF | -20 | mA | 3 | |||
| 振荡器频率 | fOSC | 1 | MHz | 3 | |||
| 工作温度 (VPC284x) | TA | -40 | 105 | ℃ | VPC284x family range, applies to VPC2845 | 3 | |
| 基准电压 VREF | VREF | 4.9 | 5 | 5.1 | V | IVREF = 1 mA, TJ = 25°C | 4 |
| 线性调整 | ΔVREF | 2 | 20 | mV | 12≤VDD≤25V | 4 | |
| 负载调整 | ΔVREF | 3 | 25 | mV | 1mA≤IVREF≤20mA | 4 | |
| 温度系数 | ΔVREF/ΔT | 0.2 | 0.4 | mV/℃ | 4 | ||
| 输出总变化 | VREF | 4.82 | 5.18 | V | 线性、负载、温度 | 4 | |
| 长期稳定性 | VREF | 5 | 25 | mV | 1000 小时,TA= 125°C | 4 | |
| 短路电流 | ISC | -30 | -50 | -70 | mA | 4 | |
| 频率 | fOSC | 49 | 52 | 55 | kHz | TA=25℃,RT=10kΩ,CT=3.3nF | 4 |
| 频率 | fOSC | 225 | 250 | 275 | kHz | TA=25℃,RT=6.2kΩ,CT=1.0nF | 4 |
| 随电压的变化 | ΔfOSC/ΔV | 0.2 | 1 | % | 12V≤VDD≤25V | 4 | |
| 随温度的变化 | ΔfOSC/ΔT | 1 | 2.5 | % | -40℃≤TA≤125℃ | 4 | |
| RT/CT 下拉电流 | Idischarge | 7.8 | 8.3 | 8.8 | mA | TJ = 25°C | 4 |
| RT/CT 下拉电流 | Idischarge | 7.6 | 9 | mA | -40℃≤TA≤125℃ | 4 | |
| FB 基准电压 | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP=2.5V, TA=25℃ | 4 |
| 输入偏置电流 | IFB | -0.1 | -1 | uA | VFB=5V | 4 | |
| 开环增益 | AVOL | 70 | 95 | dB | 2V≤VO≤4V | 4 | |
| 单位增益带宽 | BW | 0.7 | 1 | MHz | TJ = 25°C | 4 | |
| 电源信噪比 | PSRR | 60 | 70 | dB | 12V≤VDD≤25V | 4 | |
| 输入电流 (SNK) | ICOMP(SNK) | 2 | 10 | mA | VFB=2.7V,VFB=1.1V | 4 | |
| 输出电流 (SRC) | ICOMP(SRC) | -0.5 | -1 | mA | VFB=2.3V,VFB=5V | 4 | |
| VOUT 高电平 | VOH | 5.4 | 6 | 6.6 | V | VFB=2.3V,RCOMP=15kΩ到地 | 4 |
| VOUT 低电平 | VOL | 0.1 | 0.5 | V | VFB=2.7V,RCOMP=15kΩ到 8 脚 | 4 | |
| ACS 增益 | ACS | 2.85 | 3 | 3.15 | V/V | 5 | |
| 最大比较阈值电压 | VCS_th | 0.9 | 1 | 1.1 | V | VFB<2.4V | 5 |
| 输入偏置电流 | ICS | -0.1 | -2 | uA | 5 | ||
| 从 CS 到 OUT 的延迟 | tD | 30 | 65 | nS | VCS 从 0 跳变至 2V | 5 | |
| 输出低电平时的内阻 | RDSON(OL) | 4 | 10 | Ω | ISINK=200mA | 5 | |
| 输出高电平时的内阻 | RDSON(OH) | 8 | 16 | Ω | ISOURCE=200mA | 5 | |
| VDD 欠压锁定时下拉电流 | IOUT(SNK) | 100 | 300 | mA | VDD=6V,VOUT=1V | 5 | |
| 上升时间 | tr | 30 | 55 | nS | TJ=25℃,CL=1nF | 5 | |
| 下降时间 | tf | 20 | 40 | nS | TJ=25℃,CL=1nF | 5 | |
| 启动阈值电压 VPCx843/VPCx845 | VDD(ON) | 7.9 | 8.5 | 9.1 | V | 5 | |
| 欠压锁定阈值电压 VPCx843/VPCx845 | VDD(OFF) | 7.1 | 7.7 | 8.3 | V | 5 | |
| 最大占空比 VPCx844/VPCx845 | DMAX | 47 | 48 | 50 | % | 5 | |
| 最小占空比 | DMIN | 0 | 0 | % | 5 | ||
| 启动电流 | IST | 50 | 100 | uA | VDD= VDD(ON)-0.5V | 5 | |
| 静态工作电流 | IVDD | 2.7 | 3.5 | mA | VFB=VCS=0V ,VDD=VDD(ON)+0.5V | 5 | |
| 静态工作电流 (VDD=25V) | IVDD | 8 | 14 | 17 | mA | VFB=VCS=0V,VDD=25V | 5 |
| 钳位电压 | VDD(clamp) | 30 | 34 | V | IVDD=25mA | 5 |
CAD (KiCad official)
- Symbol:
VPC2845 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
vpc2845-etched.step/vpc2845-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vpc2845.step/vpc2845.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VPSC datasheet (15 pp, sha256
a3f0b7c9be78a5be, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# VPC2845
**VPSC** · DC-DC Converters · SOP-8
VPC2845 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error amplifier compensation pin: external compensation components connect here to shape the error amplifier output, and the amplifier is internally current-limited so forcing COMP to GND gives zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier used for the voltage feedback loop, where the FB lead should be kept short and stray capacitance minimized for stability. |
| 3 | CS | input | Primary-side current sense input to the PWM comparator that terminates OUT conduction, with a typical comparator threshold VCS_th of 1 V and an optional voltage ramp for voltage-mode operation. |
| 4 | RT/CT | passive | Oscillator timing pin: timing resistor RT connects from VREF and timing capacitor CT connects to GND, giving fOSC = 1.6/(RT x CT), and RT must not be less than 5 kΩ. |
| 5 | GND | power_in | Analog and signal ground, which also serves as power ground on packages without a separate PGND; keep the signal return path separate from the high-current gate-driver return path. |
| 6 | OUT | output | Push-pull gate drive output for the external MOSFET that sources and sinks up to 1 A peak and is held low while VDD is below the turn-on threshold. |
| 7 | VDD | power_in | Controller bias supply input, which should stay below the 28 V maximum recommended operating voltage (30 V absolute maximum) and be bypassed with a typical 0.1 µF capacitor placed directly at the pin. |
| 8 | VREF | power_out | 5 V reference output that requires a minimum 0.1 µF ceramic bypass capacitor placed as close to the pin as possible, with an additional bypass capacitor needed if other external loads are connected. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VPSC |
| Package | SOP-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 输入电压 VDD (absolute maximum) | VDD | | | 30 | V | | 3 |
| 输入电流 VDD | VDD | | | 30 | mA | | 3 |
| 输出峰值电流 | OUT | -1 | | 1 | A | | 3 |
| 模拟引脚对 GND (COMP、CS、FB、RT/CT) | COMP, CS, FB, RT/CT | -0.3 | | 6 | V | | 3 |
| 基准电压对 GND | VREF | | | 6.6 | V | | 3 |
| 输出引脚对 GND | OUT | -0.3 | | 30 | V | | 3 |
| 误差放大器输出吸入电流 | COMP | | | 15 | mA | | 3 |
| 最大工作结温 | TJMAX | | | 150 | ℃ | | 3 |
| ESD 人体模式 HBM | V(ESD) | -3000 | | 3000 | V | per ESDA/JEDEC JS-001-2017 | 3 |
| ESD 机器模式 CDM | V(ESD) | -1000 | | 1000 | V | per ESDA/JEDEC JS-002-2014 | 3 |
| 输入电压 VDD (recommended) | VVDD | | | 28 | V | | 3 |
| FB 基准电压 | VFB | | 2.5 | | V | | 3 |
| 电流采样输入 | VCS | | | 1 | V | | 3 |
| 电源电流 | IVDD | | | 25 | mA | | 3 |
| 输出平均电流 | IOUT | | | 200 | mA | | 3 |
| 基准电源输出电流 | IVREF | | | -20 | mA | | 3 |
| 振荡器频率 | fOSC | | | 1 | MHz | | 3 |
| 工作温度 (VPC284x) | TA | -40 | | 105 | ℃ | VPC284x family range, applies to VPC2845 | 3 |
| 基准电压 VREF | VREF | 4.9 | 5 | 5.1 | V | IVREF = 1 mA, TJ = 25°C | 4 |
| 线性调整 | ΔVREF | | 2 | 20 | mV | 12≤VDD≤25V | 4 |
| 负载调整 | ΔVREF | | 3 | 25 | mV | 1mA≤IVREF≤20mA | 4 |
| 温度系数 | ΔVREF/ΔT | | 0.2 | 0.4 | mV/℃ | | 4 |
| 输出总变化 | VREF | 4.82 | | 5.18 | V | 线性、负载、温度 | 4 |
| 长期稳定性 | VREF | | 5 | 25 | mV | 1000 小时,TA= 125°C | 4 |
| 短路电流 | ISC | -30 | -50 | -70 | mA | | 4 |
| 频率 | fOSC | 49 | 52 | 55 | kHz | TA=25℃,RT=10kΩ,CT=3.3nF | 4 |
| 频率 | fOSC | 225 | 250 | 275 | kHz | TA=25℃,RT=6.2kΩ,CT=1.0nF | 4 |
| 随电压的变化 | ΔfOSC/ΔV | | 0.2 | 1 | % | 12V≤VDD≤25V | 4 |
| 随温度的变化 | ΔfOSC/ΔT | | 1 | 2.5 | % | -40℃≤TA≤125℃ | 4 |
| RT/CT 下拉电流 | Idischarge | 7.8 | 8.3 | 8.8 | mA | TJ = 25°C | 4 |
| RT/CT 下拉电流 | Idischarge | 7.6 | | 9 | mA | -40℃≤TA≤125℃ | 4 |
| FB 基准电压 | VFB | 2.475 | 2.5 | 2.525 | V | VCOMP=2.5V, TA=25℃ | 4 |
| 输入偏置电流 | IFB | | -0.1 | -1 | uA | VFB=5V | 4 |
| 开环增益 | AVOL | 70 | 95 | | dB | 2V≤VO≤4V | 4 |
| 单位增益带宽 | BW | 0.7 | 1 | | MHz | TJ = 25°C | 4 |
| 电源信噪比 | PSRR | 60 | 70 | | dB | 12V≤VDD≤25V | 4 |
| 输入电流 (SNK) | ICOMP(SNK) | | 2 | 10 | mA | VFB=2.7V,VFB=1.1V | 4 |
| 输出电流 (SRC) | ICOMP(SRC) | | -0.5 | -1 | mA | VFB=2.3V,VFB=5V | 4 |
| VOUT 高电平 | VOH | 5.4 | 6 | 6.6 | V | VFB=2.3V,RCOMP=15kΩ到地 | 4 |
| VOUT 低电平 | VOL | | 0.1 | 0.5 | V | VFB=2.7V,RCOMP=15kΩ到 8 脚 | 4 |
| ACS 增益 | ACS | 2.85 | 3 | 3.15 | V/V | | 5 |
| 最大比较阈值电压 | VCS_th | 0.9 | 1 | 1.1 | V | VFB<2.4V | 5 |
| 输入偏置电流 | ICS | | -0.1 | -2 | uA | | 5 |
| 从 CS 到 OUT 的延迟 | tD | | 30 | 65 | nS | VCS 从 0 跳变至 2V | 5 |
| 输出低电平时的内阻 | RDSON(OL) | | 4 | 10 | Ω | ISINK=200mA | 5 |
| 输出高电平时的内阻 | RDSON(OH) | | 8 | 16 | Ω | ISOURCE=200mA | 5 |
| VDD 欠压锁定时下拉电流 | IOUT(SNK) | | 100 | 300 | mA | VDD=6V,VOUT=1V | 5 |
| 上升时间 | tr | | 30 | 55 | nS | TJ=25℃,CL=1nF | 5 |
| 下降时间 | tf | | 20 | 40 | nS | TJ=25℃,CL=1nF | 5 |
| 启动阈值电压 VPCx843/VPCx845 | VDD(ON) | 7.9 | 8.5 | 9.1 | V | | 5 |
| 欠压锁定阈值电压 VPCx843/VPCx845 | VDD(OFF) | 7.1 | 7.7 | 8.3 | V | | 5 |
| 最大占空比 VPCx844/VPCx845 | DMAX | 47 | 48 | 50 | % | | 5 |
| 最小占空比 | DMIN | 0 | 0 | | % | | 5 |
| 启动电流 | IST | | 50 | 100 | uA | VDD= VDD(ON)-0.5V | 5 |
| 静态工作电流 | IVDD | | 2.7 | 3.5 | mA | VFB=VCS=0V ,VDD=VDD(ON)+0.5V | 5 |
| 静态工作电流 (VDD=25V) | IVDD | 8 | 14 | 17 | mA | VFB=VCS=0V,VDD=25V | 5 |
| 钳位电压 | VDD(clamp) | 30 | | 34 | V | IVDD=25mA | 5 |
## CAD (KiCad official)
- Symbol: `VPC2845`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `vpc2845-etched.step` / `vpc2845-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vpc2845.step` / `vpc2845.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [VPSC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603007631728926720) (15 pp, sha256 `a3f0b7c9be78a5be`, retrieved 2026-10-15, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/vpc2845-datasheet.pdf)