component
VPC2843
Public Made by Adomby adom
VPSC DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownVPC2843
VPSC · DC-DC Converters · SOP-8
VPC2843 from VPSC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | output | Error-amplifier compensation output. External compensation network (RC) is tied here to shape the loop response of the error amplifier. Because the EA output is internally current-limited, this pin can also be pulled down externally to force zero duty cycle. |
| 2 | FB | input | Inverting input of the internal error amplifier used for output voltage feedback (V_FB = 2.5 V typ). Connected to the sensed output through an external divider to close the voltage regulation loop. |
| 3 | CS | input | Primary-side current-sense input. Connected to the current-sense resistor; when the voltage on this pin exceeds the internal threshold (~1 V), the PWM terminates the OUT drive pulse. Can also be driven by a voltage ramp to configure voltage-mode operation. |
| 4 | RT/CT | passive | Fixed-frequency oscillator timing pin. A resistor R_T from VREF and capacitor C_T from this pin to GND set the switching frequency: f_OSC ≈ 1.6 / (R_T × C_T). Minimum recommended R_T is 5 kΩ; keep traces short. |
| 5 | GND | power_in | Analog ground and power return. For this single-ground package, serves as both signal and power ground reference for all internal circuitry. |
| 6 | OUT | output | Totem-pole gate driver output for the external power MOSFET. Sources/sinks up to ±1 A peak (t_r ≈ 30 ns, t_f ≈ 20 ns into 1 nF). Held low when VDD is below the UVLO turn-on threshold. |
| 7 | VDD | power_in | Analog controller supply and gate-drive bias input. Recommended operating range up to 28 V (abs max 30 V), with an internal 34 V clamp; UVLO ON = 8.5 V typ, OFF = 7.7 V typ. Requires a 0.1 μF ceramic bypass to GND close to the pin, plus a bulk cap ≥ 10× the external MOSFET gate capacitance. |
| 8 | VREF | power_out | 5 V (±1%) internal reference output, capable of sourcing up to 20 mA (I_VREF spec, -20 mA max). Used to supply charging current to the timing resistor R_T and to bias external circuitry. Bypass with ≥ 0.1 μF ceramic close to the pin; add additional decoupling if external loads are present. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VPSC |
| Package | SOP-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
VPC2843
CAD (KiCad official)
- Symbol:
VPC2843 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
vpc2843-etched.step/vpc2843-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vpc2843.step/vpc2843.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
vpc2843.step |
122 KB | You want the bare part, or you mark your own boards. |
vpc2843-etched.step |
1.8 MB | You want the part with VPC2843 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 430 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VPSC datasheet (15 pp, sha256
a82d0e8cc13eb808, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).