component
VNH7100ASTR
Public Made by Adomby adom
STMicroelectronics Motor Driver ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownVNH7100ASTR
STMicroelectronics · Motor Driver ICs · SOIC-16
VNH7100ASTR from STMicroelectronics, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GNDA | power_in | Source of low-side switch A (ground return of half-bridge A). |
| 2 | OUTA | output | Source of high-side switch A and drain of low-side switch A, connected to motor terminal A. |
| 3 | INA | input | Clockwise input, 3 V CMOS compatible, input current -1 to 10 mA. |
| 4 | VCC | power_in | Power supply voltage, absolute maximum 38 V. |
| 5 | VCC | power_in | Power supply voltage, absolute maximum 38 V. |
| 6 | INB | input | Counter clockwise input, 3 V CMOS compatible, input current -1 to 10 mA. |
| 7 | OUTB | output | Source of high-side switch B and drain of low-side switch B, connected to motor terminal B. |
| 8 | GNDB | power_in | Source of low-side switch B (ground return of half-bridge B). |
| 9 | GNDB | power_in | Source of low-side switch B (ground return of half-bridge B). |
| 10 | OUTB | output | Source of high-side switch B and drain of low-side switch B, connected to motor terminal B. |
| 11 | PWM | input | Active-high CMOS-compatible voltage-controlled input with hysteresis that modulates the low-side FETs during their on phase for speed control, up to 20 kHz; input current -1 to 10 mA. |
| 12 | VCC | power_in | Power supply voltage, absolute maximum 38 V. |
| 13 | CS | output | Multiplexed analog sense output (MultiSense) delivering a current proportional to the motor current. |
| 14 | SEL0 | input | Active-high input compatible with 3 V and 5 V CMOS outputs that, with INA and INB, selects the CS information per the operative truth table; input current -1 to 10 mA. |
| 15 | OUTA | output | Source of high-side switch A and drain of low-side switch A, connected to motor terminal A. |
| 16 | GNDA | power_in | Source of low-side switch A (ground return of half-bridge A). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-16 |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 38 | V | 7 | |||
| Reverse DC supply voltage | -VCC | 0.3 | V | 7 | |||
| Reverse output current (continuous) | IR | -15 | A | 7 | |||
| Maximum transient supply voltage | VCCPK | 40 | V | ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 | 7 | ||
| Maximum jump start voltage for single pulse short circuit protection | VCCJS | 28 | V | 7 | |||
| Input current (INA and INB pins) | IIN | -1 | 10 | mA | 7 | ||
| SEL0 DC input current | ISEL0 | -1 | 10 | mA | 7 | ||
| PWM input current | IPWM | -1 | 10 | mA | 7 | ||
| CS pin DC output current | ISENSE | 10 | mA | VGND = VCC and VSENSE < 0 V | 7 | ||
| CS pin DC output current in reverse | ISENSE | -20 | mA | VCC < 0 V | 7 | ||
| ESD HBM (INA, INB, PWM) | VESD | 2 | kV | Human body model: R = 1.5 k; C = 100 pF | 8 | ||
| ESD HBM (VCC, Output) | VESD | 4 | kV | Human body model: R = 1.5 k; C = 100 pF | 8 | ||
| ESD CDM | VESD | 750 | V | CDM-AEC-Q100-011 | 8 | ||
| Junction operating temperature | Tc | -40 | 150 | °C | 8 | ||
| Storage temperature | TSTG | -55 | 150 | °C | 8 | ||
| Thermal resistance junction-pin HSD | Rthj-pin | 32 | °C/W | HSD | 8 | ||
| Thermal resistance junction-pin LSD | Rthj-pin | 45 | °C/W | LSD | 8 | ||
| Thermal resistance junction-ambient HSD | Rthj-amb | 40.7 | °C/W | JEDEC JESD 51-2, four-layers 2s2p PCB, HSD | 8 | ||
| Thermal resistance junction-ambient LSD | Rthj-amb | 55.4 | °C/W | JEDEC JESD 51-2, four-layers 2s2p PCB, LSD | 8 | ||
| Operating supply voltage | VCC | 4 | 28 | V | 9 | ||
| Supply current off-state (no standby) | IS | 2 | 4 | mA | INA = INB = 0; SEL0 = 5 V; PWM= 0 | 9 | |
| Supply current on-state | IS | 3.5 | 6 | mA | INA or INB = 5 V; PWM = 0 or PWM = 5; SEL0 =X | 9 | |
| Standby mode blanking time | tD_STBY | 0.2 | 1 | 1.8 | ms | VCC = 13 V; INA = INB = PMW = 0 V; VSEL0 from 5 V to 0 V | 9 |
| Static high-side resistance | RONHS | 60 | mΩ | IOUT = 2.5 A; Tj = 25°C | 9 | ||
| Static high-side resistance | RONHS | 120 | mΩ | IOUT = 2.5 A; Tj = -40 to 150°C | 9 | ||
| Static low-side resistance | RONLS | 40 | mΩ | IOUT = 2.5 A; Tj = 25°C | 9 | ||
| Static low-side resistance | RONLS | 80 | mΩ | IOUT = 2.5 A; Tj = -40°C to 150°C | 9 | ||
| Free-wheeling diode forward voltage | Vf | 0.7 | 0.9 | V | IOUT = -2.5 A; Tj = 150°C | 9 | |
| Off-state output current of one leg | IL(off) | 0.5 | µA | INA = INB = 0; PWM = 0; VCC = 13 V; Tj = 25 °C | 9 | ||
| Off-state output current of one leg | IL(off) | 3 | µA | INA = INB = 0; PWM = 0; VCC = 13 V; Tj = 125 °C | 9 | ||
| Off-state output current of one leg with other HSD on | IL(off_h) | 20 | 60 | µA | INA = 0; INB = 5 V; PWM = 0; VCC = 13 V | 9 | |
| Input low level voltage (INA, INB) | VIL | 0.9 | V | 10 | |||
| Input high level voltage (INA, INB) | VIH | 2.1 | V | 10 | |||
| Input hysteresis voltage (INA, INB) | VIHYST | 0.2 | V | 10 | |||
| Input clamp voltage (INA, INB) | VICL | 5.3 | 7.2 | V | IIN = 1 mA | 10 | |
| Input current low (INA, INB) | IINL | 1 | µA | VIN = 0.9 V | 10 | ||
| Input current high (INA, INB) | IINH | 10 | µA | VIN = 2.1 V | 10 | ||
| SEL0 input low level voltage | VSELL | 0.9 | V | VCC = 7 V up to 18 V; -40°C < Tj < 150°C | 10 | ||
| SEL0 input high level voltage | VSELH | 2.1 | V | VCC = 7 V up to 18 V; -40°C < Tj < 150°C | 10 | ||
| SEL0 high level input current | ISELH | 10 | µA | VSEL = 2.1 V | 10 | ||
| SEL0 input clamp voltage | VSELCL | 5.3 | 7.5 | V | ISEL = 1 mA | 10 | |
| PWM input low level voltage | VPWM | 0.9 | V | VCC = 7 V up to 28 V; -40°C < Tj < 150°C | 10 | ||
| PWM input high level voltage | VPWM | 2.1 | V | VCC = 7 V up to 28 V; -40°C < Tj < 150°C | 10 | ||
| PWM high level input current | IPWMH | 10 | µA | VPWM = 2.1 V | 10 | ||
| PWM input clamp voltage | VPMWCL | 5.3 | 7.2 | V | IPWM = 1 mA | 10 | |
| PWM frequency | f | 0 | 20 | kHz | VCC = 13 V; RLOAD = 5.2 Ω | 10 | |
| Turn-on delay time | td(on) | 20 | µs | Input rise time < 1µs (see Figure 6) | 10 | ||
| Turn-off delay time | td(off) | 13 | µs | Input rise time < 1µs (see Figure 6) | 10 | ||
| Rise time | tr | 0.7 | 1.5 | µs | See Figure 5 | 10 | |
| Fall time | tf | 0.2 | 0.5 | µs | See Figure 5 | 10 | |
| Low-side turn-on delay time | tcross | 40 | 150 | 350 | µs | Input rise time < 1 µs (see Figure 7) | 10 |
CAD (KiCad official)
- Symbol:
VNH7100ASTR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
vnh7100astr-etched.step/vnh7100astr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vnh7100astr.step/vnh7100astr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (38 pp, sha256
1d2921a8226c98c8, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).