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Initial commit: component/vnd10n06tr-e

Ray ·3f783208e6 ·1mo ago
2 files changed +152
README.mdadded+39
@@ -0,0 +1,39 @@+# VND10N06TR-E++**STMicroelectronics** · Power Distribution Switches · DPAK++VND10N06TR-E from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Input | input | Logic level gate input with internal Schmitt trigger; input threshold voltages VIL = 1.5V minimum and VIH = 3.2V maximum; supply current IISS = 150-300 µA at VDS = 0V and VIN = 5V. |+| 2 | Drain | output | Power MOSFET drain terminal with drain-source voltage internally clamped to 60V nominal (range 50-70V), drain current internally limited to 10A nominal (range 6-15A), and on-resistance RDS(on) = 0.3Ω maximum at VIN = 7V, ID = 1A, Tj < 125°C. |+| 3 | Source | power_in | Power MOSFET source terminal serving as the current return path and common reference point for input and output voltage measurements and internal protection circuits. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | DPAK |+| Category | Power Management (PMIC) |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `VND10N06TR-E`+- Footprint: `Package_TO_SOT_SMD:TO-252-2`+- 3D model: DPAK (KiCad packages3D, STEP)+- 3D model files: `vnd10n06tr-e-etched.step` / `vnd10n06tr-e-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vnd10n06tr-e.step` / `vnd10n06tr-e.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588927075830386688) (25 pp, sha256 `3c9fa02c73e7b512`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/vnd10n06tr-e-datasheet.pdf)
page.jsonadded+113
@@ -0,0 +1,113 @@+{+  "slug": "vnd10n06tr-e",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics Power Distribution Switches, DPAK. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "vnd10n06tr-e",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "vnd10n06tr-e.kicad_sym",+    "vnd10n06tr-e.kicad_mod",+    "vnd10n06tr-e.glb",+    "vnd10n06tr-e.step",+    "vnd10n06tr-e.lbr",+    "docs/hero.png",+    "docs/vnd10n06tr-e-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "VND10N06TR-E",+    "manufacturer": "STMicroelectronics",+    "package": "DPAK",+    "pin_count": 3,+    "category": "Power Management (PMIC)",+    "subcategory": "Power Distribution Switches",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588927075830386688",+    "parts": {+      "symbol": "vnd10n06tr-e.kicad_sym",+      "footprint": "vnd10n06tr-e.kicad_mod",+      "model_3d": "vnd10n06tr-e-etched.glb",+      "model_3d_plain": "vnd10n06tr-e.glb",+      "model_3d_step": "vnd10n06tr-e-etched.step",+      "model_3d_step_plain": "vnd10n06tr-e.step",+      "lbr": "vnd10n06tr-e.lbr"+    },+    "distributor_links": {+      "lcsc": "C2149912"+    },+    "pins": [+      {+        "number": "1",+        "name": "Input",+        "type": "input",+        "description": "Logic level gate input with internal Schmitt trigger; input threshold voltages VIL = 1.5V minimum and VIH = 3.2V maximum; supply current IISS = 150-300 µA at VDS = 0V and VIN = 5V."+      },+      {+        "number": "2",+        "name": "Drain",+        "type": "output",+        "description": "Power MOSFET drain terminal with drain-source voltage internally clamped to 60V nominal (range 50-70V), drain current internally limited to 10A nominal (range 6-15A), and on-resistance RDS(on) = 0.3Ω maximum at VIN = 7V, ID = 1A, Tj < 125°C."+      },+      {+        "number": "3",+        "name": "Source",+        "type": "power_in",+        "description": "Power MOSFET source terminal serving as the current return path and common reference point for input and output voltage measurements and internal protection circuits."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Block diagram with explicit pin descriptions referenced on PAGE 5 is not provided in the datasheet t"+        ],+        "pages_sent": 25,+        "cost_usd": 0.3327,+        "at": "2026-09-23T18:28:39"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588927075830386688",+        "pages": 25,+        "sha256": "3c9fa02c73e7b512",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 3,+        "described": 3,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file