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VL102-Q4
Public Made by Adomby adom
VIA Labs USB Converters, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownVL102-Q4
VIA Labs · USB Converters · QFN-48-EP(6x6)
VL102-Q4 from VIA Labs, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD5IN | power_in | 5V power input for the Vconn power output. |
| 2 | CC1_D | bidirectional | DRP port configuration channel 1. |
| 3 | CC2_D | bidirectional | DRP port configuration channel 2. |
| 4 | ODV5DP | output | Open-drain I/O for 5V video power control. |
| 5 | AUXP | bidirectional | DP AUX channel positive. |
| 6 | AUXN | bidirectional | DP AUX channel negative. |
| 7 | HPD | input | DP hot plug detect input. |
| 8 | SBU1 | bidirectional | Sideband use 1; the built-in SBU1/SBU2 switch supports USB-C cable flipping, and no further electrical limits are stated. |
| 9 | SBU2 | bidirectional | Sideband use 2; the built-in SBU1/SBU2 switch supports USB-C cable flipping, and no further electrical limits are stated. |
| 10 | CC2_U | bidirectional | Charging UFP configuration channel 2. |
| 11 | CC1_U | bidirectional | Charging UFP configuration channel 1. |
| 12 | VBUS_DET2 | input | USB-C DRP Vbus voltage detector input. |
| 13 | VBUS_DET1 | input | USB-C charging UFP Vbus voltage detector input. |
| 14 | REXT | passive | Analog bias pin; connect to an external 20.5 kΩ resistor (+/-1% accuracy). |
| 15 | VCONNIN33 | power_in | 3.3V Vconn power input; recommended operating range 3.0 V to 3.6 V (3.3 V typical). |
| 16 | LDOVDD5 | power_in | 5V input for the 5V-to-3.3V LDO; recommended range 4.5 V to 5.5 V (5 V typical). |
| 17 | LDOVDD33O | power_out | 3.3V output of the 5V-to-3.3V LDO; output 3.135 V to 3.465 V with max output current 100 mA. |
| 18 | OSCVDD18O | power_out | Analog 1.8V power output; output voltage 1.71 V to 1.89 V from the internal 3.3V-to-1.8V LDO, max output current 100 mA. |
| 19 | OSCXI | input | 24 MHz crystal input. |
| 20 | OSCXO | output | 24 MHz crystal output. |
| 21 | BOOST_VTRL | input | Boost voltage control input. |
| 22 | CS_N | input | Current sensing negative input. |
| 23 | CS_P | input | Current sensing positive input. |
| 24 | DP_IN | bidirectional | D+ data line connected to the downstream facing port. |
| 25 | DM_IN | bidirectional | D- data line connected to the downstream facing port. |
| 26 | DM_OUT | bidirectional | D- data line connected to the upstream facing port. |
| 27 | DP_OUT | bidirectional | D+ data line connected to the upstream facing port. |
| 28 | DM_U | bidirectional | D- data line to the USB Billboard device. |
| 29 | DP_U | bidirectional | D+ data line to the USB Billboard device. |
| 30 | VCC33 | power_in | Digital 3.3V I/O power input; recommended range 3.0 V to 3.6 V (3.3 V typical). |
| 31 | GPIO9 | bidirectional | General purpose I/O for application customization. |
| 32 | GPIO8 | bidirectional | General purpose I/O for application customization. |
| 33 | GPIO7 | bidirectional | General purpose I/O for application customization. |
| 34 | GPIO6 | bidirectional | General purpose I/O for application customization. |
| 35 | GPIO5 | bidirectional | General purpose I/O for application customization. |
| 36 | GPIO3 | bidirectional | General purpose I/O for application customization. |
| 37 | VDD5V | power_in | E-fuse power input, connected to 3.3V in normal use. |
| 38 | VCC33 | power_in | Digital 3.3V I/O power input; recommended range 3.0 V to 3.6 V (3.3 V typical). |
| 39 | GPIO4 | bidirectional | General purpose I/O for application customization. |
| 40 | DVCC18 | power_in | Digital 1.8V core power input; recommended range 1.62 V to 1.98 V (1.8 V typical). |
| 41 | GPIO1 | bidirectional | General purpose I/O for application customization. |
| 42 | GPIO2 | bidirectional | General purpose I/O for application customization. |
| 43 | RESET_ | input | External chip reset input. |
| 44 | TESTEN | input | Test mode enable with internal pull-down; do not connect for normal operation. |
| 45 | SPI_CS_ | output | Serial flash chip enable. |
| 46 | SPI_Q | input | Serial flash data output (input to the VL102). |
| 47 | SPI_CLK | output | Serial flash clock. |
| 48 | SPI_D | output | Serial flash data input (driven by the VL102). |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VIA Labs |
| Package | QFN-48-EP(6x6) |
| Category | Interface |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TSTG | -55 | 125 | °C | 12 | ||
| 3.3V Power Input Voltage | VDD33 | -0.5 | 3.69 | V | 12 | ||
| 5V Power Input Voltage | VDD50 | -0.5 | 5.5 | V | 12 | ||
| Output Voltage at any output (printed max: VCC+ 0.5) | VO | -0.5 | V | 12 | |||
| Electrostatic Discharge | VESD | -2 | 2 | kV | Human Body Model | 12 | |
| 5V to 3.3V LDO 5V Power Input | LDOVDD5 | 4.5 | 5 | 5.5 | V | 12 | |
| 3.3V Vconn power input | VCONNIN33 | 3 | 3.3 | 3.6 | V | 12 | |
| Digital IO power 3.3V | VCC33 | 3 | 3.3 | 3.6 | V | 12 | |
| Digital Core power 1.8V | DVCC18 | 1.62 | 1.8 | 1.98 | V | 12 | |
| Ambient Temperature | TA | 0 | 70 | °C | 12 | ||
| Input Low Voltage | VIL | -0.3 | 0.8 | V | 12 | ||
| Input High Voltage | VIH | 2 | 3.6 | V | 12 | ||
| Output Low Voltage | VOL | 0.4 | V | IOL=15.8mA | 12 | ||
| Output High Voltage | VOH | 2.4 | V | IOH=26.5mA | 12 | ||
| Input Leakage Current | IIL | -10 | 10 | µA | 0<VIN<VCC | 12 | |
| Tristate Leakage Current | IOZ | -10 | 10 | µA | 0<VOUT<VCC | 12 | |
| Internal 3.3V to 1.8V LDO Input Voltage | 3 | 3.3 | 3.6 | V | 12 | ||
| Internal 3.3V to 1.8V LDO Output Voltage | 1.71 | 1.8 | 1.89 | V | 12 | ||
| Internal 3.3V to 1.8V LDO Max. Output Current | 100 | mA | 12 | ||||
| Internal 3.3V to 1.8V LDO Output Voltage Tolerance | -5 | 5 | % | 12 | |||
| Internal 5V to 3.3V LDO Input Voltage | 4.5 | 5 | 5.5 | V | 13 | ||
| Internal 5V to 3.3V LDO Output Voltage | 3.135 | 3.3 | 3.465 | V | 13 | ||
| Internal 5V to 3.3V LDO Max. Output Current | 100 | mA | 13 | ||||
| Internal 5V to 3.3V LDO Output Voltage Tolerance | -5 | 5 | % | 13 | |||
| PD BMC Voltage Swing | VBMCSWING | 1.05 | 1.2 | V | 13 | ||
| PD BMC Drive Output Resistance | ZBMCDRV | 33 | 75 | Ω | 13 | ||
| PD BMC Rise Time | TBMCR | 300 | ns | 13 | |||
| PD BMC Fall Time | TBMCF | 300 | ns | 13 | |||
| USB Full-speed Input High | VFSIH | 2 | V | 13 | |||
| USB Full-speed Input Low | VFSIL | 0.8 | V | 13 | |||
| USB Full-speed Differential Common Mode Voltage | VFSCM | 0.8 | 2.5 | V | 13 | ||
| USB Full-speed Output Low | VFSOL | 0 | 0.3 | V | 13 | ||
| USB Full-speed Output High | VFSOH | 2.8 | 3.6 | V | 13 | ||
| USB Full-speed Rise Time | TFSR | 4 | 20 | ns | 13 | ||
| USB Full-speed Fall Time | TFSF | 4 | 20 | ns | 13 | ||
| USB Full-speed Output Signal Crossover Voltage | VFSCRS | 1.3 | 2 | V | 13 | ||
| High-speed squelch detection threshold | VHSSQ | 100 | 150 | mV | 13 | ||
| High-speed data signaling common mode voltage | VHSCM | -50 | 500 | mV | 13 | ||
| High-speed idle level | VHSOI | -10 | 10 | mV | 13 | ||
| High-speed data high | VHSOH | 360 | 440 | mV | 13 | ||
| High-speed data low | VHSOL | -10 | 10 | mV | 13 | ||
| Chirp J level | VCHIRPJ | 700 | 1100 | mV | 13 | ||
| Chirp K level | VCHIRPK | -900 | -500 | mV | 13 | ||
| High-speed Drive output resistance | ZHSDRV | 40.5 | 49.5 | Ω | 13 | ||
| High-speed Rise Time | THSR | 500 | ps | 13 | |||
| High-speed Fall Time | THSF | 500 | ps | 13 |
CAD (KiCad official)
- Symbol:
VL102-Q4 - Footprint:
Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm - 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
vl102-q4-etched.step/vl102-q4-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vl102-q4.step/vl102-q4.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VIA Labs datasheet (16 pp, sha256
e766bde769e9c0e9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).