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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	23d ago
viewers	viper115lstr: viewers · Ray	23d ago
package.json	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
page.json	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
README.md	Publish 0.1.0 · Ray	23d ago
viper115lstr-etched.glb	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
viper115lstr-etched.step	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
viper115lstr-hero.glb	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
viper115lstr-hero.overlay.json	viper115lstr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	16d ago
viper115lstr.glb	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	16d ago
viper115lstr.kicad_mod	Publish 0.1.0 · Ray	23d ago
viper115lstr.kicad_sym	Publish 0.1.0 · Ray	23d ago
viper115lstr.lbr	Publish 0.1.0 · Ray	23d ago
viper115lstr.step	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	16d ago

VIPER115LSTR

STMicroelectronics · AC-DC Controllers And Regulators · SOP-10

VIPER115LSTR from STMicroelectronics, in a SOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground and source of the internal MOSFET and return of the device bias current; all bias-component grounds must be tied to a trace going to this pin, separate from the pulsed current return.
2	VCC	power_in	Controller supply (4.5 V to 30 V operating range) needing an external storage capacitor to GND, also fed by the internal HV current source for startup charging, with a 0.1 µF typ. bypass capacitor recommended close to the IC.
3	DIS	input	Disable input: if voltage exceeds VDIS_th (1.2 V typ.) for more than tDEB (1 ms typ.) the PWM is disabled for tDIS_RESTART (500 ms typ.) in auto-restart, used for input/output overvoltage protection via a divider, and must be soldered to GND if unused.
4	FB	input	Direct feedback, inverting input of the internal transconductance E/A referenced to 1.2 V with respect to GND, fed by the output divider (or VCC divider for primary regulation), and the E/A is disabled by soldering FB to GND.
5	COMP	output	Compensation, output of the internal E/A, with a compensation network to GND for loop stability, or driven directly by the optocoupler (E/A disabled) in secondary feedback to set the DRAIN peak current setpoint.
6	DRAIN	passive	MOSFET drain (800 V max), internal HV current source sinks current from it to charge VCC at startup, mechanically connected to the internal metal pad, with copper area required under these pins for heat dissipation.
7	DRAIN	passive	MOSFET drain (800 V max), internal HV current source sinks current from it to charge VCC at startup, mechanically connected to the internal metal pad, with copper area required under these pins for heat dissipation.
8	DRAIN	passive	MOSFET drain (800 V max), internal HV current source sinks current from it to charge VCC at startup, mechanically connected to the internal metal pad, with copper area required under these pins for heat dissipation.
9	DRAIN	passive	MOSFET drain (800 V max), internal HV current source sinks current from it to charge VCC at startup, mechanically connected to the internal metal pad, with copper area required under these pins for heat dissipation.
10	DRAIN	passive	MOSFET drain (800 V max), internal HV current source sinks current from it to charge VCC at startup, mechanically connected to the internal metal pad, with copper area required under these pins for heat dissipation.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOP-10
Category	Power Management (PMIC)
Pins	10

CAD (KiCad official)

Symbol: VIPER115LSTR
Footprint: Package_SO:SOIC-10_3.9x4.9mm_P1mm
3D model: SOP-10, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.75 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: viper115lstr-etched.step / viper115lstr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); viper115lstr.step / viper115lstr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (37 pp, sha256 c43ec45622596607, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF