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VIPER115HSTR

STMicroelectronics · AC-DC Controllers And Regulators · SOP-10

VIPER115HSTR from STMicroelectronics, in a SOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground and MOSFET source connection; return path for bias current; all bias component groundings must be connected to this pin and kept separate from pulsed current return.
2 VCC power_in Controller supply voltage (4.5 V to 30 V); external storage capacitor required across VCC and GND; 0.1 µF bypass capacitor typ. recommended close to IC for noise filtering.
3 DIS input Disable input; PWM disables when voltage exceeds internal threshold VDIS_th (1.2 V typ.) for more than tDEB (1 ms typ.) with auto-restart after tDIS_RESTART (500 msec typ.); solder to GND if function not required.
4 FB input Direct feedback inverting input of internal transconductance error amplifier referenced to 1.2 V with respect to GND; accepts output voltage through voltage divider; solder to GND to disable error amplifier.
5 COMP output Error amplifier output; compensation network placed between this pin and GND to achieve control loop stability and dynamic performance; driven directly by optocoupler in secondary feedback mode.
6 DRAIN power_in High voltage MOSFET drain input (rated to 800 V, 2 A pulsed current); internal high voltage current source sinks current to charge VCC at startup and during steady-state; PCB copper area required under all DRAIN pins for thermal dissipation.
7 DRAIN power_in High voltage MOSFET drain input (rated to 800 V, 2 A pulsed current); internal high voltage current source sinks current to charge VCC at startup and during steady-state; PCB copper area required under all DRAIN pins for thermal dissipation.
8 DRAIN power_in High voltage MOSFET drain input (rated to 800 V, 2 A pulsed current); internal high voltage current source sinks current to charge VCC at startup and during steady-state; PCB copper area required under all DRAIN pins for thermal dissipation.
9 DRAIN power_in High voltage MOSFET drain input (rated to 800 V, 2 A pulsed current); internal high voltage current source sinks current to charge VCC at startup and during steady-state; PCB copper area required under all DRAIN pins for thermal dissipation.
10 DRAIN power_in High voltage MOSFET drain input (rated to 800 V, 2 A pulsed current); internal high voltage current source sinks current to charge VCC at startup and during steady-state; PCB copper area required under all DRAIN pins for thermal dissipation.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOP-10
Category Power Management (PMIC)
Pins 10

CAD (KiCad official)

  • Symbol: VIPER115HSTR
  • Footprint: Package_SO:SOIC-10_3.9x4.9mm_P1mm
  • 3D model: SOP-10, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.75 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: viper115hstr-etched.step / viper115hstr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); viper115hstr.step / viper115hstr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (37 pp, sha256 c43ec45622596607, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF