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VBZA4611

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VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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VBZA4611

VBsemi Elec · MOSFETs · SO-8

VBZA4611 from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of the N-channel MOSFET (60 V VDS, 5.3 A ID at TC = 25 °C, RDS(on) 0.026 Ω at VGS = 10 V).
2 G1 input Gate of the N-channel MOSFET, rated for VGS ±20 V with VGS(th) 1 to 3 V.
3 S2 passive Source of the P-channel MOSFET (-60 V VDS, RDS(on) 0.055 Ω at VGS = -10 V).
4 G2 input Gate of the P-channel MOSFET, rated for VGS ±20 V with VGS(th) -1 to -3 V.
5 D2 passive Drain of the P-channel MOSFET (-60 V VDS, pulsed drain current -25 A); pins 5 and 6 are both D2.
6 D2 passive Drain of the P-channel MOSFET (-60 V VDS, pulsed drain current -25 A); pins 5 and 6 are both D2.
7 D1 passive Drain of the N-channel MOSFET (60 V VDS, pulsed drain current 20 A); pins 7 and 8 are both D1.
8 D1 passive Drain of the N-channel MOSFET (60 V VDS, pulsed drain current 20 A); pins 7 and 8 are both D1.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage N-Ch VDS 60 V TA = 25 °C 1
Drain-Source Voltage P-Ch VDS -60 V TA = 25 °C 1
Gate-Source Voltage VGS -20 20 V TA = 25 °C 1
Pulsed Drain Current N-Ch IDM 20 A 10 µs pulse width 1
Pulsed Drain Current P-Ch IDM -25 A 10 µs pulse width 1
Single Pulse Avalanche Current N-Ch IAS 11 A L = 0.1 mH 1
Single Pulse Avalanche Current P-Ch IAS 15 A L = 0.1 mH 1
Maximum Power Dissipation N-Ch PD 2 W TA = 25 °C, surface mounted on 1" x 1" FR4, t = 10 s 1
Maximum Power Dissipation P-Ch PD 2 W TA = 25 °C, surface mounted on 1" x 1" FR4, t = 10 s 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Junction-to-Ambient N-Ch RthJA 55 62.5 °C/W t ≤ 10 s 1
Junction-to-Ambient P-Ch RthJA 53 62.5 °C/W t ≤ 10 s 1
Junction-to-Foot (Drain) N-Ch RthJF 33 40 °C/W Steady State 1
Junction-to-Foot (Drain) P-Ch RthJF 30 37 °C/W Steady State 1
Drain-Source Breakdown Voltage N-Ch VDS 60 V VGS = 0 V, ID = 250 µA 2
Drain-Source Breakdown Voltage P-Ch VDS -60 V VGS = 0 V, ID = - 250 µA 2
Gate Threshold Voltage N-Ch VGS(th) 1 3 V VDS = VGS, ID = 250 µA 2
Gate Threshold Voltage P-Ch VGS(th) -1 -3 V VDS = VGS, ID = - 250 µA 2
Gate-Body Leakage N-Ch IGSS 100 nA VDS = 0 V, VGS = ± 20 V 2
Gate-Body Leakage P-Ch IGSS -100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current N-Ch IDSS 1 µA VDS = 60 V, VGS = 0 V 2
Zero Gate Voltage Drain Current P-Ch IDSS -1 µA VDS = - 60 V, VGS = 0 V 2
Zero Gate Voltage Drain Current N-Ch IDSS 10 µA VDS = 60 V, VGS = 0 V, TJ = 55 °C 2
Zero Gate Voltage Drain Current P-Ch IDSS -10 µA VDS = - 60 V, VGS = 0 V, TJ = 55 °C 2
On-State Drain Current N-Ch ID(on) 20 A VDS ≥ 5 V, VGS = 10 V 2
On-State Drain Current P-Ch ID(on) -25 A VDS ≤ - 5 V, VGS = - 10 V 2
Total Gate Charge N-Ch Qg 13 20 nC VDS = 30 V, VGS = 10 V, ID = 4.3 A 2
Total Gate Charge P-Ch Qg 14.5 22 nC VDS = - 30 V, VGS = - 10 V, ID = - 3.1 A 2
Total Gate Charge N-Ch Qg 6 9 nC VDS = 30 V, VGS = 4.5 V, ID = 4.3 A 2
Total Gate Charge P-Ch Qg 8 12 nC VDS = - 30 V, VGS = - 4.5 V, ID = - 3.1 A 2
Gate Resistance N-Ch Rg 2 3 Ω f = 1 MHz 2
Gate Resistance P-Ch Rg 14 20 Ω f = 1 MHz 2
Turn-On Delay Time N-Ch td(on) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
Turn-On Delay Time P-Ch td(on) 30 45 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Rise Time N-Ch tr 65 100 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
Rise Time P-Ch tr 70 105 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Turn-Off Delay Time N-Ch td(off) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
Turn-Off Delay Time P-Ch td(off) 40 60 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Fall Time N-Ch tf 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω 3
Fall Time P-Ch tf 30 45 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω 3
Turn-On Delay Time N-Ch td(on) 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
Turn-On Delay Time P-Ch td(on) 10 15 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
Rise Time N-Ch tr 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
Rise Time P-Ch tr 13 20 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
Turn-Off Delay Time N-Ch td(off) 20 30 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω 3
Turn-Off Delay Time P-Ch td(off) 35 55 ns VDD = - 30 V, RL = 12.5 Ω, ID ≅ - 2.4 A, VGEN = - 10 V, Rg = 1 Ω 3
Body Diode Voltage N-Ch VSD 0.8 1.2 V IS = 1.7 A 3
Body Diode Voltage P-Ch VSD -0.8 -1.2 V IS = - 2 A 3
Body Diode Reverse Recovery Time N-Ch trr 30 60 ns IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Time P-Ch trr 30 50 ns IF = - 2 A, dI/dt = - 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Charge N-Ch Qrr 32 50 nC IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C 3
Body Diode Reverse Recovery Charge P-Ch Qrr 35 60 nC IF = - 2 A, dI/dt = - 100 A/µs, TJ = 25 °C 3

CAD (KiCad official)

  • Symbol: VBZA4611
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: vbza4611-etched.step / vbza4611-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vbza4611.step / vbza4611.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (14 pp, sha256 e3555b14c9e0914d, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF