component

UTM4052L-S08-R-VB

Public Made by Adom

by adom

VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsutm4052l-s08-r-vbfactory-2.0.0extractor-text

Verified UTM4052L-S08-R-VB

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: UTM4052L-S08-R-VB · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 14-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-be0y9bgm/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ utm4052l-s08-r-vb.kicad_sym✓ utm4052l-s08-r-vb.kicad_mod✓ utm4052l-s08-r-vb.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
utm4052l-s08-r-vb / README.md
History Download
Ray Publish 0.1.0 e138888 5d ago

UTM4052L-S08-R-VB

VBsemi Elec · MOSFETs · SO-8

UTM4052L-S08-R-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive N-channel MOSFET source terminal; the N-channel drain-source voltage is rated 60 V and gate-source voltage ±20 V.
2 G1 input N-channel MOSFET gate terminal; gate-source voltage is rated ±20 V.
3 S2 passive P-channel MOSFET source terminal; the P-channel drain-source voltage is rated -60 V and gate-source voltage ±20 V.
4 G2 input P-channel MOSFET gate terminal; gate-source voltage is rated ±20 V.
5 D2 passive P-channel MOSFET drain terminal; the P-channel continuous drain current is rated -4.9 A at TA = 25 °C for the device.
6 D2 passive P-channel MOSFET drain terminal, internally connected to pin 5; the P-channel drain-source voltage is rated -60 V.
7 D1 passive N-channel MOSFET drain terminal; the N-channel continuous drain current is rated 5.3 A at TC = 25 °C.
8 D1 passive N-channel MOSFET drain terminal, internally connected to pin 7; the N-channel drain-source voltage is rated 60 V.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 60 V N-Channel 1
Drain-Source Voltage VDS -60 V P-Channel 1
Gate-Source Voltage VGS -20 20 V 1
Pulsed Drain Current IDM 20 A 10 µs pulse width, N-Channel 1
Pulsed Drain Current IDM -25 A 10 µs pulse width, P-Channel 1
Maximum Power Dissipation PD 3.1 W TC = 25 °C, N-Channel 1
Maximum Power Dissipation PD 3.4 W TC = 25 °C, P-Channel 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Drain-Source Breakdown Voltage VDS 60 V VGS = 0 V, ID = 250 µA, N-Ch 2
Drain-Source Breakdown Voltage VDS -60 V VGS = 0 V, ID = -250 µA, P-Ch 2
Gate Threshold Voltage VGS(th) 1 3 V VDS = VGS, ID = 250 µA, N-Ch 2
Gate Threshold Voltage VGS(th) -1 -3 V VDS = VGS, ID = -250 µA, P-Ch 2
Gate-Body Leakage IGSS 100 nA VDS = 0 V, VGS = ±20 V, N-Ch 2
Gate-Body Leakage IGSS -100 nA VDS = 0 V, VGS = ±20 V, P-Ch 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 60 V, VGS = 0 V, N-Ch 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS = -60 V, VGS = 0 V, P-Ch 2
Zero Gate Voltage Drain Current IDSS 10 µA VDS = 60 V, VGS = 0 V, TJ = 55 °C, N-Ch 2
Zero Gate Voltage Drain Current IDSS -10 µA VDS = -60 V, VGS = 0 V, TJ = 55 °C, P-Ch 2
On-State Drain Current ID(on) 20 A VDS ≥ 5 V, VGS = 10 V, N-Ch 2
On-State Drain Current ID(on) -25 A VDS ≤ -5 V, VGS = -10 V, P-Ch 2
Drain-Source On-State Resistance RDS(on) 0.055 Ω VGS = -10 V, ID = -3.1 A, P-Ch 2
Drain-Source On-State Resistance RDS(on) 0.029 Ω VGS = 4.5 V, ID = 3.9 A, N-Ch 2
Drain-Source On-State Resistance RDS(on) 0.06 Ω VGS = -4.5 V, ID = -0.2 A, P-Ch 2
Body Diode Voltage VSD 0.8 1.2 V IS = 1.7 A, N-Ch 3
Body Diode Voltage VSD -0.8 -1.2 V IS = -2 A, P-Ch 3
Total Gate Charge Qg 13 20 nC VDS = 30 V, VGS = 10 V, ID = 4.3 A, N-Ch 2
Total Gate Charge Qg 14.5 22 nC VDS = -30 V, VGS = -10 V, ID = -3.1 A, P-Ch 2
Total Gate Charge Qg 6 9 nC VDS = 30 V, VGS = 4.5 V, ID = 4.3 A, N-Ch 2
Total Gate Charge Qg 8 12 nC VDS = -30 V, VGS = -4.5 V, ID = -3.1 A, P-Ch 2
Gate Resistance Rg 2 3 Ω f = 1 MHz, N-Ch 2
Gate Resistance Rg 14 20 Ω f = 1 MHz, P-Ch 2
Body Diode Reverse Recovery Time trr 30 60 ns IF = 1.7 A, dI/dt = 100 A/µs, TJ = 25 °C, N-Ch 3
Body Diode Reverse Recovery Time trr 30 50 ns IF = -2 A, dI/dt = -100 A/µs, TJ = 25 °C, P-Ch 3
Body Diode Reverse Recovery Charge Qrr 32 50 nC N-Ch 3
Body Diode Reverse Recovery Charge Qrr 35 60 nC P-Ch 3
Turn-On Delay Time td(on) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω, N-Ch 3
Turn-On Delay Time td(on) 30 45 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -4.5 V, Rg = 1 Ω, P-Ch 3
Rise Time tr 65 100 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω, N-Ch 3
Rise Time tr 70 105 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -4.5 V, Rg = 1 Ω, P-Ch 3
Turn-Off Delay Time td(off) 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω, N-Ch 3
Turn-Off Delay Time td(off) 40 60 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -4.5 V, Rg = 1 Ω, P-Ch 3
Fall Time tf 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 4.5 V, Rg = 1 Ω, N-Ch 3
Fall Time tf 30 45 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -4.5 V, Rg = 1 Ω, P-Ch 3
Turn-On Delay Time td(on) 10 15 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω, N-Ch 3
Rise Time tr 15 25 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω, N-Ch 3
Rise Time tr 13 20 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -10 V, Rg = 1 Ω, P-Ch 3
Turn-Off Delay Time td(off) 20 30 ns VDD = 30 V, RL = 8.8 Ω, ID ≅ 3.4 A, VGEN = 10 V, Rg = 1 Ω, N-Ch 3
Turn-Off Delay Time td(off) 35 55 ns VDD = -30 V, RL = 12.5 Ω, ID ≅ -2.4 A, VGEN = -10 V, Rg = 1 Ω, P-Ch 3
Maximum Junction-to-Ambient RthJA 55 62.5 °C/W t ≤ 10 s, N-Channel 1
Maximum Junction-to-Ambient RthJA 53 62.5 °C/W t ≤ 10 s, P-Channel 1
Maximum Junction-to-Foot (Drain) RthJF 33 40 °C/W Steady State, N-Channel 1
Maximum Junction-to-Foot (Drain) RthJF 30 37 °C/W Steady State, P-Channel 1

CAD (KiCad official)

  • Symbol: UTM4052L-S08-R-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: utm4052l-s08-r-vb-etched.step / utm4052l-s08-r-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); utm4052l-s08-r-vb.step / utm4052l-s08-r-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (14 pp, sha256 8e02505e4b9b2f9e, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF