component
UT9564G-SO8-R
Public Made by Adomby adom
UTC Unisonic Tech MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
UT9564G-SO8-R
UTC Unisonic Tech · MOSFETs · SOP-8
UT9564G-SO8-R from UTC Unisonic Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 4 | G | input | Gate terminal of the MOSFET; the datasheet rates the gate-source voltage at ±25 V (VGS). |
| 5 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 6 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 7 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 8 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC Unisonic Tech |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -40 | V | 3 | |||
| Gate-Source Voltage | VGS | -25 | 25 | V | 3 | ||
| Continuous Drain Current | ID | -7.3 | A | TA=25°C | 3 | ||
| Continuous Drain Current | ID | -5.9 | A | TA=70°C | 3 | ||
| Pulsed Drain Current | IDM | -30 | A | Note 1: pulse width limited by max junction temperature | 3 | ||
| Power Dissipation | PD | 2.5 | W | TA=25°C | 3 | ||
| Junction Temperature | TJ | -55 | 150 | °C | 3 | ||
| Storage Temperature | TSTG | -55 | 150 | °C | 3 | ||
| Drain-Source Breakdown Voltage | BVDSS | -40 | V | ID=-250µA, VGS=0V | 3 | ||
| Drain-Source Leakage Current | IDSS | -1 | µA | VDS=-40V, VGS=0V, TJ=25°C | 3 | ||
| Drain-Source Leakage Current | IDSS | -25 | µA | VDS=-32V, VGS=0V, TJ=70°C | 3 | ||
| Gate-Source Leakage Current | IGSS | -100 | 100 | nA | VGS=±25V | 3 | |
| Gate Threshold Voltage | VGS(TH) | -1 | -3 | V | VDS=VGS, ID=-250µA | 3 | |
| Input Capacitance | CISS | 2240 | 3600 | pF | 3 | ||
| Total Gate Charge | QG | 27 | 43 | nC | 3 | ||
| Maximum Body-Diode Continuous Current | IS | -7.3 | A | 3 | |||
| Maximum Body-Diode Pulsed Current | ISM | -30 | A | 3 | |||
| Thermal Resistance Junction to Ambient (SOP-8) | θJA | 50 | °C/W | Surface mounted on 1 in² copper pad of FR4 board, t ≤10sec | 3 | ||
| Thermal Resistance Junction to Ambient (minimum copper pad) | θJA | 125 | °C/W | Mounted on minimum copper pad | 3 | ||
| Linear Derating Factor | 0.02 | W/°C | 3 | ||||
| Breakdown Voltage Temperature Coefficient | △BVDSS/ T △ J | -0.03 | V/°C | Reference to 25°C, ID=-1mA | 3 | ||
| Static Drain-Source On-State Resistance | RDS(ON) | 28 | mΩ | VGS=-10V, ID=-7A | 3 | ||
| Static Drain-Source On-State Resistance | RDS(ON) | 40 | mΩ | VGS=-4.5V, ID=-5A | 3 | ||
| Forward Transconductance | gFS | 13 | S | VDS=-10V, ID=-7A | 3 | ||
| Output Capacitance | COSS | 300 | pF | 3 | |||
| Reverse Transfer Capacitance | CRSS | 250 | pF | VGS=0V, VDS=-25V, f=1.0MHz | 3 | ||
| Gate to Source Charge | QGS | 6 | nC | 3 | |||
| Gate to Drain Charge | QGD | 14 | nC | VGS=-4.5V, VDS=-32V, ID=-7A | 3 | ||
| Turn-ON Delay Time | tD(ON) | 14 | ns | 3 | |||
| Rise Time | tR | 8 | ns | 3 | |||
| Turn-OFF Delay Time | tD(OFF) | 46 | ns | 3 | |||
| Fall-Time | tF | 17 | ns | VGS=-10V, VDS=-20V, ID=-1A, RG=3.3Ω, RD=20Ω | 3 | ||
| Drain-Source Diode Forward Voltage | VSD | -1.2 | V | IS=-2A, VGS=0V | 3 | ||
| Reverse Recovery Time | tRR | 144 | ns | 3 | |||
| Reverse Recovery Charge | QRR | 110 | nC | IS=-7A, VGS=0V, dI/dt=100A/µs | 3 |
CAD (KiCad official)
- Symbol:
UT9564G-SO8-R - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ut9564g-so8-r-etched.step/ut9564g-so8-r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ut9564g-so8-r.step/ut9564g-so8-r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UTC Unisonic Tech datasheet (4 pp, sha256
6a1253dcd0b44587, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# UT9564G-SO8-R
**UTC Unisonic Tech** · MOSFETs · SOP-8
UT9564G-SO8-R from UTC Unisonic Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are all source and are tied together on the SOP-8 package. |
| 4 | G | input | Gate terminal of the MOSFET; the datasheet rates the gate-source voltage at ±25 V (VGS). |
| 5 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 6 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 7 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
| 8 | D | passive | Drain terminal of the MOSFET; pins 5 through 8 are all drain and are tied together on the SOP-8 package, with drain-source voltage rated at -40 V (VDS). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UTC Unisonic Tech |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -40 | | | V | | 3 |
| Gate-Source Voltage | VGS | -25 | | 25 | V | | 3 |
| Continuous Drain Current | ID | -7.3 | | | A | TA=25°C | 3 |
| Continuous Drain Current | ID | -5.9 | | | A | TA=70°C | 3 |
| Pulsed Drain Current | IDM | -30 | | | A | Note 1: pulse width limited by max junction temperature | 3 |
| Power Dissipation | PD | | | 2.5 | W | TA=25°C | 3 |
| Junction Temperature | TJ | -55 | | 150 | °C | | 3 |
| Storage Temperature | TSTG | -55 | | 150 | °C | | 3 |
| Drain-Source Breakdown Voltage | BVDSS | -40 | | | V | ID=-250µA, VGS=0V | 3 |
| Drain-Source Leakage Current | IDSS | | | -1 | µA | VDS=-40V, VGS=0V, TJ=25°C | 3 |
| Drain-Source Leakage Current | IDSS | | | -25 | µA | VDS=-32V, VGS=0V, TJ=70°C | 3 |
| Gate-Source Leakage Current | IGSS | -100 | | 100 | nA | VGS=±25V | 3 |
| Gate Threshold Voltage | VGS(TH) | -1 | | -3 | V | VDS=VGS, ID=-250µA | 3 |
| Input Capacitance | CISS | | 2240 | 3600 | pF | | 3 |
| Total Gate Charge | QG | | 27 | 43 | nC | | 3 |
| Maximum Body-Diode Continuous Current | IS | -7.3 | | | A | | 3 |
| Maximum Body-Diode Pulsed Current | ISM | -30 | | | A | | 3 |
| Thermal Resistance Junction to Ambient (SOP-8) | θJA | | 50 | | °C/W | Surface mounted on 1 in² copper pad of FR4 board, t ≤10sec | 3 |
| Thermal Resistance Junction to Ambient (minimum copper pad) | θJA | | 125 | | °C/W | Mounted on minimum copper pad | 3 |
| Linear Derating Factor | | | 0.02 | | W/°C | | 3 |
| Breakdown Voltage Temperature Coefficient | △BVDSS/ T △ J | | -0.03 | | V/°C | Reference to 25°C, ID=-1mA | 3 |
| Static Drain-Source On-State Resistance | RDS(ON) | | 28 | | mΩ | VGS=-10V, ID=-7A | 3 |
| Static Drain-Source On-State Resistance | RDS(ON) | | 40 | | mΩ | VGS=-4.5V, ID=-5A | 3 |
| Forward Transconductance | gFS | | 13 | | S | VDS=-10V, ID=-7A | 3 |
| Output Capacitance | COSS | | 300 | | pF | | 3 |
| Reverse Transfer Capacitance | CRSS | | 250 | | pF | VGS=0V, VDS=-25V, f=1.0MHz | 3 |
| Gate to Source Charge | QGS | | 6 | | nC | | 3 |
| Gate to Drain Charge | QGD | | 14 | | nC | VGS=-4.5V, VDS=-32V, ID=-7A | 3 |
| Turn-ON Delay Time | tD(ON) | | 14 | | ns | | 3 |
| Rise Time | tR | | 8 | | ns | | 3 |
| Turn-OFF Delay Time | tD(OFF) | | 46 | | ns | | 3 |
| Fall-Time | tF | | 17 | | ns | VGS=-10V, VDS=-20V, ID=-1A, RG=3.3Ω, RD=20Ω | 3 |
| Drain-Source Diode Forward Voltage | VSD | | -1.2 | | V | IS=-2A, VGS=0V | 3 |
| Reverse Recovery Time | tRR | | 144 | | ns | | 3 |
| Reverse Recovery Charge | QRR | | 110 | | nC | IS=-7A, VGS=0V, dI/dt=100A/µs | 3 |
## CAD (KiCad official)
- Symbol: `UT9564G-SO8-R`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ut9564g-so8-r-etched.step` / `ut9564g-so8-r-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ut9564g-so8-r.step` / `ut9564g-so8-r.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UTC Unisonic Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175054727667712) (4 pp, sha256 `6a1253dcd0b44587`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ut9564g-so8-r-datasheet.pdf)