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USB5744T-I

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Microchip Tech USB Converters, VQFN-56-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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USB5744T-I

Microchip Tech · USB Converters · VQFN-56-EP(7x7)

USB5744T-I from Microchip Tech, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USB2DN_DP1/PRT_DIS_P1 bidirectional USB 2.0 downstream port 1 D+ data line, which doubles as the PRT_DIS_P1 strap that disables port 1 only when tied to 3.3 V together with PRT_DIS_M1.
2 USB2DN_DM1/PRT_DIS_M1 bidirectional USB 2.0 downstream port 1 D- data line, which doubles as the PRT_DIS_M1 strap that disables port 1 only when tied to 3.3 V together with PRT_DIS_P1.
3 USB3DN_TXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data plus; leave floating if unused.
4 USB3DN_TXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data minus; leave floating if unused.
5 VDD12 power_in +1.2 V core power supply pin.
6 USB3DN_RXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data plus; leave floating if unused.
7 USB3DN_RXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data minus; leave floating if unused.
8 USB2DN_DP2/PRT_DIS_P2 bidirectional USB 2.0 downstream port 2 D+ data line, which doubles as the PRT_DIS_P2 strap that disables port 2 only when tied to 3.3 V together with PRT_DIS_M2.
9 USB2DN_DM2/PRT_DIS_M2 bidirectional USB 2.0 downstream port 2 D- data line, which doubles as the PRT_DIS_M2 strap that disables port 2 only when tied to 3.3 V together with PRT_DIS_P2.
10 USB3DN_TXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data plus; leave floating if unused.
11 USB3DN_TXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data minus; leave floating if unused.
12 VDD12 power_in +1.2 V core power supply pin.
13 USB3DN_RXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data plus; leave floating if unused.
14 USB3DN_RXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data minus; leave floating if unused.
15 VDD12 power_in +1.2 V core power supply pin.
16 VDD33 power_in +3.3 V power and internal regulator input.
17 USB2DN_DP3/PRT_DIS_P3 bidirectional USB 2.0 downstream port 3 D+ data line, which doubles as the PRT_DIS_P3 strap that disables port 3 only when tied to 3.3 V together with PRT_DIS_M3.
18 USB2DN_DM3/PRT_DIS_M3 bidirectional USB 2.0 downstream port 3 D- data line, which doubles as the PRT_DIS_M3 strap that disables port 3 only when tied to 3.3 V together with PRT_DIS_P3.
19 USB3DN_TXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data plus; leave floating if unused.
20 USB3DN_TXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data minus; leave floating if unused.
21 VDD12 power_in +1.2 V core power supply pin.
22 USB3DN_RXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data plus; leave floating if unused.
23 USB3DN_RXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data minus; leave floating if unused.
24 USB2DN_DP4/PRT_DIS_P4 bidirectional USB 2.0 downstream port 4 D+ data line, which doubles as the PRT_DIS_P4 strap that disables port 4 only when tied to 3.3 V together with PRT_DIS_M4.
25 USB2DN_DM4/PRT_DIS_M4 bidirectional USB 2.0 downstream port 4 D- data line, which doubles as the PRT_DIS_M4 strap that disables port 4 only when tied to 3.3 V together with PRT_DIS_P4.
26 USB3DN_TXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data plus; leave floating if unused.
27 USB3DN_TXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data minus; leave floating if unused.
28 VDD12 power_in +1.2 V core power supply pin.
29 USB3DN_RXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data plus; leave floating if unused.
30 USB3DN_RXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data minus; leave floating if unused.
31 VDD33 power_in +3.3 V power and internal regulator input.
32 PRT_CTL4/GANG_PWR bidirectional Port 4 power enable (active-high output) / overcurrent sense (input), and when pulled high it enables gang mode with this pin as the gang power pin; leave floating if unused.
33 VDD12 power_in +1.2 V core power supply pin.
34 PRT_CTL3 bidirectional Port 3 power enable (active-high output) / overcurrent sense (input) from an external current monitor on USB port 3; leave floating if unused.
35 PRT_CTL2 bidirectional Port 2 power enable (active-high output) / overcurrent sense (input) from an external current monitor on USB port 2; leave floating if unused.
36 PRT_CTL1 bidirectional Port 1 power enable (active-high output) / overcurrent sense (input) from an external current monitor on USB port 1; leave floating if unused.
37 VBUS_DET input Detects the upstream bus power state; for a detachable hub it must be connected to upstream VBUS through a 50 kΩ by 100 kΩ resistor divider to provide 3.3 V.
38 SPI_CLK/SMCLK bidirectional SPI clock output to the serial ROM in SPI mode, or open-drain SMBus clock (12 mA sink) when configured for SMBus slave operation.
39 SPI_DO/SMDAT bidirectional SPI data output in SPI mode, or SMBus data I/O (12 mA sink) when configured for SMBus slave operation.
40 SPI_DI/CFG_BC_EN bidirectional SPI data input in SPI mode, and a battery charging configuration strap whose resistor value selects the battery-charging ports per Table 3-13.
41 SPI_CE_N/CFG_NON_REM bidirectional Active-low SPI chip enable output in SPI mode, and a non-removable port configuration strap whose resistor value selects the non-removable ports per Table 3-12.
42 RESET_N input Active-low reset input (Schmitt-triggered) that puts the device into Reset Mode, and asserting it low enters Standby Mode.
43 VDD12 power_in +1.2 V core power supply pin.
44 VDD33 power_in +3.3 V power and internal regulator input.
45 USB2UP_DP bidirectional USB 2.0 upstream data plus (D+) line.
46 USB2UP_DM bidirectional USB 2.0 upstream data minus (D-) line.
47 USB3UP_TXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data plus.
48 USB3UP_TXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data minus.
49 VDD12 power_in +1.2 V core power supply pin.
50 USB3UP_RXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data plus.
51 USB3UP_RXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data minus.
52 ATEST passive Analog test pin that must always be connected to ground.
53 XTALO output External 25 MHz crystal output; leave unconnected when CLK_IN is driven by a single-ended clock oscillator.
54 XTALI/CLK_IN input External 25 MHz crystal input, or external reference clock input when driven by a single-ended clock oscillator (suggested 25 MHz, 50% duty cycle ±10%, ±100 ppm, jitter < 100 ps RMS).
55 VDD33 power_in +3.3 V power and internal regulator input.
56 RBIAS passive A 12.0 kΩ (±1%) resistor from this pin to ground sets the transceiver's internal bias settings.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-56-EP(7x7)
Category Interface
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
+1.2 V Supply Voltage (VDD12) absolute maximum VDD12 -0.5 1.32 V Note 1 32
+3.3 V Supply Voltage (VDD33) absolute maximum VDD33 -0.5 4.6 V Note 1 32
Positive voltage on input signal pins, with respect to ground 4.6 V Note 2 32
Negative voltage on input signal pins, with respect to ground -0.5 V 32
Positive voltage on XTALI/CLK_IN, with respect to ground XTALI/CLK_IN 3.63 V 32
Positive voltage on USB DP/DM signal pins, with respect to ground DP/DM 6 V 32
Positive voltage on USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground USB3UP_xxxx, USB3DN_xxxx 1.32 V 32
Storage Temperature -55 150 °C 32
Junction Temperature 125 °C 32
HBM ESD Performance 3 kV HBM 32
+1.2 V Supply Voltage (VDD12) operating VDD12 1.08 1.32 V 32
+3.3 V Supply Voltage (VDD33) operating VDD33 3 3.6 V 32
Input Signal Pins Voltage -0.3 3.6 V Note 2 32
XTALI/CLK_IN Voltage XTALI/CLK_IN -0.3 3.6 V 32
USB 2.0 DP/DM Signal Pins Voltage DP/DM -0.3 5.5 V 32
USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx Signal Pins Voltage USB3UP_xxxx, USB3DN_xxxx -0.3 1.32 V 32
Ambient Operating Temperature in Still Air (industrial version) TA -40 85 °C Industrial version, Note 3 32
+1.2 V Supply Voltage Rise Time TRT 5 ms Figure 10-1 32
+3.3 V Supply Voltage Rise Time TRT 5 ms Figure 10-1 32
High-level input voltage, I type input buffer VIH 2.1 V 35
Low-level input voltage, I type input buffer VIL 0.9 V 35
High-level input voltage, IS type (Schmitt-trigger) input buffer VIH 1.9 V 35
Low-level input voltage, IS type (Schmitt-trigger) input buffer VIL 0.9 V 35
Schmitt trigger hysteresis, IS type input buffer (VIHT - VILT) VHYS 9 20 40 mV 35
Low output level, O6 type output buffer VOL 0.4 V IOL = 6 mA 35
Low output level, O12 type output buffer VOL 0.4 V IOL = 12 mA 35
Low output level, OD12 type open-drain output buffer VOL 0.4 V IOL = 12 mA 35
Low input level, ICLK type input buffer (XTALI input) VIL 0.5 V Note 4 35
High input level, ICLK type input buffer (XTALI input) VIH 0.85 V Note 4 35
VDD12 to VDD33 rise time tVDD33 0 ms 36
VDD33 to RESET_N/VBUS_DET rise time treset 0 ms 36
Configuration strap hold after external power supplies at operational levels tcsh 1 ms 36
RESET_N input assertion time trstia 5 s 37
Configuration strap pins hold after RESET_N deassertion tcsh 1 ms 37
SPI clock frequency tfc 30 MHz 30 MHz operation 38
Chip enable (SPI_CE_N) high time tceh 100 ns 30 MHz operation 38
Clock to input data tclq 13 ns 30 MHz operation 38
Input data hold time tdh 0 ns 30 MHz operation 38
Output setup time tos 5 ns 30 MHz operation 38
Output hold time toh 5 ns 30 MHz operation 38
Clock to output valid tov 4 ns 30 MHz operation 38
Chip enable (SPI_CE_N) low to first clock tcel 12 ns 30 MHz operation 38
Last clock to chip enable (SPI_CE_N) high tceh 12 ns 30 MHz operation 38
SPI clock frequency tfc 60 MHz 60 MHz operation 38
Chip enable (SPI_CE_N) high time tceh 50 ns 60 MHz operation 38
Clock to input data tclq 9 ns 60 MHz operation 38
Maximum power dissipation PD(max) 1400 mW 33
Junction-to-ambient thermal resistance, still air JA 30 °C/W 0 m/s airflow 33
Junction-to-ambient thermal resistance, airflow JA 26 °C/W 1 m/s airflow 33
Junction-to-top characterization parameter, still air JT 0.2 °C/W 0 m/s airflow 33
Junction-to-top characterization parameter, airflow JT 0.3 °C/W 1 m/s airflow 33
Junction-to-case thermal resistance, still air JC 2.6 °C/W 0 m/s airflow 33
Junction-to-case thermal resistance, airflow JC 2.6 °C/W 1 m/s airflow 33

CAD (KiCad official)

  • Symbol: USB5744T-I
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: usb5744t-i-etched.step / usb5744t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb5744t-i.step / usb5744t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (51 pp, sha256 b000b915ca780ce6, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF