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USB5734T-I

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Microchip Tech USB ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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USB5734T-I

Microchip Tech · USB ICs · QFN-64-EP(9x9)

USB5734T-I from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CFG_STRAP input Device mode configuration strap, latched at POR and RESET_N rising edge, where an external resistor selects one of six modes.
2 USB2DN_DP1/PRT_DIS_P1 bidirectional USB 2.0 downstream port 1 D+ data line, also the port 1 D+ disable strap that must be tied to 3.3 V with PRT_DIS_M1 to disable the port.
3 USB2DN_DM1/PRT_DIS_M1 bidirectional USB 2.0 downstream port 1 D- data line, also the port 1 D- disable strap used with PRT_DIS_P1.
4 USB3DN_TXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data plus, leave floating if unused.
5 USB3DN_TXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed transmit data minus, leave floating if unused.
6 VDD12 power_in +1.2 V core power supply pin.
7 USB3DN_RXDP1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data plus, leave floating if unused.
8 USB3DN_RXDM1 bidirectional USB 3.2 Gen 1 downstream port 1 SuperSpeed receive data minus, leave floating if unused.
9 USB2DN_DP2/PRT_DIS_P2 bidirectional USB 2.0 downstream port 2 D+ data line, also the port 2 D+ disable strap used with PRT_DIS_M2.
10 USB2DN_DM2/PRT_DIS_M2 bidirectional USB 2.0 downstream port 2 D- data line, also the port 2 D- disable strap used with PRT_DIS_P2.
11 USB3DN_TXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data plus, leave floating if unused.
12 USB3DN_TXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed transmit data minus, leave floating if unused.
13 VDD12 power_in +1.2 V core power supply pin.
14 USB3DN_RXDP2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data plus, leave floating if unused.
15 USB3DN_RXDM2 bidirectional USB 3.2 Gen 1 downstream port 2 SuperSpeed receive data minus, leave floating if unused.
16 PROG_FUNC7 bidirectional Programmable function pin 7, whose function is set by CFG_STRAP (USB2_SUSP_IND in Configuration 1), with an O10 buffer of 10 mA sink and source.
17 VDD12 power_in +1.2 V core power supply pin.
18 VDD33 power_in +3.3 V power and internal regulator input.
19 USB2DN_DP3/PRT_DIS_P3 bidirectional USB 2.0 downstream port 3 D+ data line, also the port 3 D+ disable strap used with PRT_DIS_M3.
20 USB2DN_DM3/PRT_DIS_M3 bidirectional USB 2.0 downstream port 3 D- data line, also the port 3 D- disable strap used with PRT_DIS_P3.
21 USB3DN_TXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data plus, leave floating if unused.
22 USB3DN_TXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed transmit data minus, leave floating if unused.
23 VDD12 power_in +1.2 V core power supply pin.
24 USB3DN_RXDP3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data plus, leave floating if unused.
25 USB3DN_RXDM3 bidirectional USB 3.2 Gen 1 downstream port 3 SuperSpeed receive data minus, leave floating if unused.
26 USB2DN_DP4/PRT_DIS_P4 bidirectional USB 2.0 downstream port 4 D+ data line, also the port 4 D+ disable strap used with PRT_DIS_M4.
27 USB2DN_DM4/PRT_DIS_M4 bidirectional USB 2.0 downstream port 4 D- data line, also the port 4 D- disable strap used with PRT_DIS_P4.
28 USB3DN_TXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data plus, leave floating if unused.
29 USB3DN_TXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed transmit data minus, leave floating if unused.
30 VDD12 power_in +1.2 V core power supply pin.
31 USB3DN_RXDP4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data plus, leave floating if unused.
32 USB3DN_RXDM4 bidirectional USB 3.2 Gen 1 downstream port 4 SuperSpeed receive data minus, leave floating if unused.
33 VDD33 power_in +3.3 V power and internal regulator input.
34 PRT_CTL4/GANG_PWR input Port 4 power enable and overcurrent sense; when pulled high it enables gang mode with GANG_PWR as the gang power pin.
35 VDD12 power_in +1.2 V core power supply pin.
36 PRT_CTL3 input Port 3 power enable (active high output) and overcurrent sense input from an external current monitor, leave floating if unused.
37 PRT_CTL2 input Port 2 power enable (active high output) and overcurrent sense input from an external current monitor, leave floating if unused.
38 PRT_CTL1 input Port 1 power enable (active high output) and overcurrent sense input from an external current monitor, leave floating if unused.
39 PROG_FUNC2 bidirectional Programmable function pin 2, whose function is set by CFG_STRAP, with an O6 buffer of 6 mA sink and source.
40 PROG_FUNC3 bidirectional Programmable function pin 3, whose function is set by CFG_STRAP, with an I/O12 buffer of 12 mA sink and source.
41 VBUS_DET/GPIO16 input Detects upstream bus power; must be connected to VBUS through a 50 k/100 k divider to provide 3.3 V on a detachable hub.
42 SPI_CLK/UART_RX/GPIO4/I2C_SLV_CFG0 bidirectional SPI clock output to the serial ROM (O6), UART receive in UART mode, GPIO4, and I2C slave 0 configuration strap.
43 SPI_DO/UART_TX/GPIO5/I2C_SLV_CFG1 bidirectional SPI data output (O6), UART transmit (O12), GPIO5, and I2C slave 1 configuration strap, with a 10 k pull-down selecting UART mode.
44 SPI_DI/GPIO9/CFG_BC_EN bidirectional SPI data input (Schmitt-triggered), GPIO9 (I/O12), and battery charging configuration strap CFG_BC_EN.
45 SPI_CE_N/GPIO7/CFG_NON_REM bidirectional Active low SPI chip enable output (O12), GPIO7, and non-removable port configuration strap CFG_NON_REM.
46 PROG_FUNC4 bidirectional Programmable function pin 4, which is SMDAT (OD12) in Configurations 1, 2, 3 and 6, with an I/O12 buffer of 12 mA.
47 PROG_FUNC5 bidirectional Programmable function pin 5, which is SMCLK (OD12) in Configurations 1, 2, 3 and 6, with an I/O12 buffer of 12 mA.
48 RESET_N input Active low reset input (Schmitt-triggered) that puts the device into Standby Mode and latches configuration straps on its rising edge.
49 PROG_FUNC6 bidirectional Programmable function pin 6, whose function is set by CFG_STRAP, with an I/O12 buffer of 12 mA sink and source.
50 PROG_FUNC1 bidirectional Programmable function pin 1, whose function is set by CFG_STRAP, with an I/O12 buffer of 12 mA sink and source.
51 VDD12 power_in +1.2 V core power supply pin.
52 VDD33 power_in +3.3 V power and internal regulator input.
53 USB2UP_DP bidirectional USB 2.0 upstream data plus (D+) with internal 1M pull-down.
54 USB2UP_DM bidirectional USB 2.0 upstream data minus (D-) with internal 1M pull-down.
55 USB3UP_TXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data plus.
56 USB3UP_TXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed transmit data minus.
57 VDD12 power_in +1.2 V core power supply pin.
58 USB3UP_RXDP bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data plus.
59 USB3UP_RXDM bidirectional USB 3.2 Gen 1 upstream SuperSpeed receive data minus.
60 ATEST passive Analog test pin that must always be connected to ground.
61 XTALO output External 25 MHz crystal output, left unconnected when an external clock oscillator drives XTALI/CLK_IN.
62 XTALI/CLK_IN input External 25 MHz crystal input, or external reference clock input from a single-ended clock oscillator.
63 VDD33 power_in +3.3 V power and internal regulator input.
64 RBIAS passive A 12.0 k (+/- 1%) resistor is attached from ground to this pin to set the transceiver internal bias.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient operating temperature TA -40 85 °C Industrial version (-I), Note 3 42
+1.2 V supply voltage VDD12 1.08 1.32 V 42
+3.3 V supply voltage VDD33 3 3.6 V 42
Input signal pins voltage -0.3 3.6 V Note 2 42
XTALI/CLK_IN voltage -0.3 3.6 V 42
USB 2.0 DP/DM signal pins voltage -0.3 5.5 V 42
USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins voltage -0.3 1.32 V 42
+1.2 V supply voltage rise time TRT 5 ms Figure 10-1 42
+3.3 V supply voltage rise time TRT 5 ms Figure 10-1 42
+1.2 V supply voltage (VDD12) absolute maximum VDD12 -0.5 1.32 V Note 1 42
+3.3 V supply voltage (VDD33) absolute maximum VDD33 -0.5 4.6 V Note 1 42
Positive voltage on input signal pins, with respect to ground 4.6 V Note 2 42
Negative voltage on input signal pins, with respect to ground -0.5 V 42
Positive voltage on XTALI/CLK_IN, with respect to ground 3.63 V 42
Positive voltage on USB DP/DM signal pins, with respect to ground 6 V 42
Positive voltage on USB 3.2 Gen 1 USB3UP_xxxx and USB3DN_xxxx signal pins, with respect to ground 1.32 V 42
Storage temperature -55 150 °C 42
Junction temperature 125 °C 42
Thermal resistance junction-to-ambient JA 25 °C/W 0 m/s airflow 43
Thermal resistance junction-to-ambient JA 22 °C/W 1 m/s airflow 43
Thermal characteristic junction-to-top-center JT 0.2 °C/W 0 m/s airflow 43
Thermal characteristic junction-to-top-center JT 0.3 °C/W 1 m/s airflow 43
Thermal resistance junction-to-case JC 2.5 °C/W 0 m/s airflow 43
Maximum power dissipation PD(max) 1400 mW 43
O6 buffer low output level VOL 0.4 V IOL = 6 mA 45
O10 buffer low output level VOL 0.4 V IOL = 10 mA 45
O12 buffer low output level VOL 0.4 V IOL = 12 mA 45
OD12 buffer low output level VOL 0.4 V IOL = 12 mA 45
Schmitt trigger hysteresis (PROG_FUNC3 pin) VHYS 10 60 mV PROG_FUNC3 pin, Note 4 45
Crystal frequency tolerance at 25 °C Ftol -50 50 PPM Note 7 49
Crystal frequency stability over temperature Ftemp -50 50 PPM Note 7 49
Total allowable PPM budget -100 100 PPM Note 8 49
Equivalent series resistance R1 50 Ω Crystal 49
Crystal drive level PW 100 uW Crystal 49
Input clock duty cycle 40 50 60 % Single-ended clock oscillator input 49
External reference clock frequency tolerance -100 100 ppm CLK_IN, suggested 49
External reference clock duty cycle tolerance -10 10 % CLK_IN 50% duty cycle, suggested 49

CAD (KiCad official)

  • Symbol: USB5734T-I
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: usb5734t-i-etched.step / usb5734t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb5734t-i.step / usb5734t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (61 pp, sha256 46a04562738d5cf2, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF