USB4604I-1080HN from Microchip Tech, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Battery power supply input that feeds the internal 3.3V regulator and needs a 4.7 uF (<1 ohm ESR) capacitor to ground placed close to the device.
2	NC	unconnected	No connect pin that must be left floating for normal device operation.
3	USBDN1_DM/PRT_DIS_M1	bidirectional	Downstream USB Port 1 D- data signal (swappable with upstream Port 0) that also serves as the Port 1 D- disable strap, which must be tied to VDD33 together with PRT_DIS_P1 at reset to disable the port.
4	USBDN1_DP/PRT_DIS_P1	bidirectional	Downstream USB Port 1 D+ data signal (swappable with upstream Port 0) that also serves as the Port 1 D+ disable strap, which must be tied to VDD33 together with PRT_DIS_M1 at reset to disable the port.
5	USBDN2_DM/PRT_DIS_M2	bidirectional	Downstream USB Port 2 D- data signal that also serves as the Port 2 D- disable strap, which must be tied to VDD33 together with PRT_DIS_P2 at reset to disable the port.
6	USBDN2_DP/PRT_DIS_P2	bidirectional	Downstream USB Port 2 D+ data signal that also serves as the Port 2 D+ disable strap, which must be tied to VDD33 together with PRT_DIS_M2 at reset to disable the port.
7	NC	unconnected	No connect pin that must be left floating for normal device operation.
8	USBDN3_DM/PRT_DIS_M3	bidirectional	Downstream USB Port 3 D- data signal that also serves as the Port 3 D- disable strap, which must be tied to VDD33 together with PRT_DIS_P3 at reset to disable the port.
9	USBDN3_DP/PRT_DIS_P3	bidirectional	Downstream USB Port 3 D+ data signal that also serves as the Port 3 D+ disable strap, which must be tied to VDD33 together with PRT_DIS_M3 at reset to disable the port.
10	USBDN4_DM/PRT_DIS_M4	bidirectional	Downstream USB Port 4 D- data signal that also serves as the Port 4 D- disable strap, which must be tied to VDD33 together with PRT_DIS_P4 at reset to disable the port.
11	USBDN4_DP/PRT_DIS_P4	bidirectional	Downstream USB Port 4 D+ data signal that also serves as the Port 4 D+ disable strap, which must be tied to VDD33 together with PRT_DIS_M4 at reset to disable the port.
12	VDDA33	power_in	+3.3V analog power supply that needs a 1.0 uF (<1 ohm ESR) capacitor to ground placed close to the device.
13	SOF	output	O8 output (8 mA sink and source) of an 8KHz clock synchronized with the USB Host SOF, controlled by the SOF_ENABLE bit in the UTIL_CONFIG1 register.
14	SUSPEND	output	Indicates that the entire hub has entered the USB suspend state so VBUS current consumption should be reduced, and must be enabled via the Protouch configuration tool.
15	PRTPWR1/PRTCTL1	bidirectional	O8 Port 1 power enable output (0 = power disabled, 1 = power enabled) that, when configured as PRTCTL1 (OD8/IS with pull-up), combines the power enable output and the over-current sense input.
16	OCS1_N	input	Active-low Schmitt input with internal pull-up from an external current monitor indicating an over-current condition on USB Port 1.
17	VDDCR12	power_in	+1.2V core power supply that needs a 1.0 uF (<1 ohm ESR) capacitor to ground in single supply applications or dual supply applications where 1.2V is not used.
18	VDD33	power_in	+3.3V power supply pin that must be connected to VDDA33.
19	PRTPWR2/PRTCTL2	bidirectional	O8 Port 2 power enable output (0 = power disabled, 1 = power enabled) that, when configured as PRTCTL2 (OD8/IS with pull-up), combines the power enable output and the over-current sense input.
20	OCS2_N	input	Active-low Schmitt input with internal pull-up from an external current monitor indicating an over-current condition on USB Port 2.
21	PRTPWR3/PRTCTL3	bidirectional	O8 Port 3 power enable output (0 = power disabled, 1 = power enabled) that, when configured as PRTCTL3 (OD8/IS with pull-up), combines the power enable output and the over-current sense input.
22	NC	unconnected	No connect pin that must be left floating for normal device operation.
23	NC	unconnected	No connect pin that must be left floating for normal device operation.
24	SPI_DI	input	SPI data input with a 50 uA (typical) internal pull-down.
25	SPI_CE_N	output	Active-low SPI chip enable output (O12, 12 mA sink and source) that is driven high in powerdown states if the SPI is enabled.
26	SPI_DO/SPI_SPD_SEL	output	SPI data output (O12) that also latches the SPI speed strap at reset (0 = 30MHz default, 1 = 60MHz) with a 50 uA (typical) internal pull-down.
27	SPI_CLK	output	SPI clock output (O12, 12 mA sink and source).
28	UART_RX/OCS3_N	input	Internal UART receive input (3.3V signal, external 12V translator required for RS232) shared with the active-low Port 3 over-current sense input with internal pull-up.
29	PRTPWR4/PRTCTL4	bidirectional	O8 Port 4 power enable output (0 = power disabled, 1 = power enabled) that, when configured as PRTCTL4 (OD8/IS with pull-up), combines the power enable output and the over-current sense input.
30	UART_TX/OCS4_N	bidirectional	Internal UART transmit output (O8, 3.3V signal, external 12V driver required for RS232) shared with the active-low Port 4 over-current sense input with internal pull-up.
31	SDA/SMBDATA	bidirectional	I2C or SMBus bidirectional serial data (IS/OD8 buffer, 8 mA open-drain sink).
32	VDD33	power_in	+3.3V power supply pin that must be connected to VDDA33.
33	SCL/SMBCLK	input	I2C serial clock input or SMBus serial clock input (I_SMB buffer).
34	NC	unconnected	No connect pin that must be left floating for normal device operation.
35	RESET_N	input	Active-low system reset input that requires a pulse at least 5us wide to reset the device.
36	VBUS_DET	input	Detects the state of upstream bus power and must be connected through a resistor divider (50k by 100k) to provide 3.3V when designing a detachable hub.
37	VDDA33	power_in	+3.3V analog power supply that needs a 1.0 uF (<1 ohm ESR) capacitor to ground placed close to the device.
38	VDD12	power_in	+1.2V HSIC power supply input, tied to VDDCR12 for HSIC operation.
39	FLEX_HSIC_UP_STROBE	bidirectional	Upstream HSIC Port 0 STROBE signal, which can optionally be swapped with the downstream Port 1 signals.
40	FLEX_USBUP_DM/PRT_DIS_M0	bidirectional	Upstream USB Port 0 D- data signal (swappable with downstream Port 1) that also serves as the Port 0 D- disable strap, with both PRT_DIS_P0 and PRT_DIS_M0 tied to VDD33 at reset to place Port 0 into HSIC mode.
41	FLEX_USBUP_DP/PRT_DIS_P0	bidirectional	Upstream USB Port 0 D+ data signal (swappable with downstream Port 1) that also serves as the Port 0 D+ disable strap, with both PRT_DIS_P0 and PRT_DIS_M0 tied to VDD33 at reset to place Port 0 into HSIC mode.
42	FLEX_HSIC_UP_DATA	bidirectional	Upstream HSIC Port 0 DATA signal, which can optionally be swapped with the downstream Port 1 signals.
43	XTAL2	output	External 24 MHz crystal output, left unconnected when XTAL1/REFCLK is driven by a single-ended clock oscillator.
44	XTAL1/REFCLK	input	External 24 MHz crystal input or single-ended reference clock input.
45	NC	unconnected	No connect pin that must be left floating for normal device operation.
46	RBIAS	passive	A 12.0k (+/-1%) resistor from ground to this pin sets the transceiver's internal bias settings.
47	VDDCOREREG	power_in	+1.8-3.3V core power supply input to the internal +1.2V regulator, which needs a 4.7 uF (<1 ohm ESR) capacitor to ground in dual supply configurations.
48	VDDA33	power_in	+3.3V analog power supply that needs a 1.0 uF (<1 ohm ESR) capacitor to ground placed close to the device.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	VQFN-48-EP(7x7)
Category	Interface ICs
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VBAT Supply Voltage		0		5.5	V	Note 9-1	39
VDDCOREREG Supply Voltage		0		3.6	V	Note 9-1	39
Positive voltage on input signal pins, with respect to ground				3.6	V	Note 9-2	39
Negative voltage on input signal pins, with respect to ground		-0.5			V	Note 9-3	39
Positive voltage on USB DP/DM signals, with respect to ground				5.5	V	Note 9-4, applies only when VDD33 is powered	39
Storage Temperature		-55		150	oC		39
VBAT Supply Voltage		3		5.5	V		40
VDDCOREREG Supply Voltage		1.6		2	V	Note 9-5, connected to external +1.8V power supply	40
VDDCOREREG Supply Voltage		3		3.6	V	Note 9-5, connected to VDD33	40
Power Supply Rise Time	tRT(max)			10	ms	RESET_N asserted at power-on (Note 9-6)	40
Power Supply Rise Time	tRT(max)			1	ms	RESET_N not used at power-on, tied high (Note 9-6)	40
Ambient Operating Temperature in Still Air	TA	-40		85	oC	Industrial version (Note 9-7)	40
Suspend supply current, single supply, USB upstream	IVBAT		320	2000	uA	Suspend; typical @ 25oC, industrial MAX	41
Standby supply current, single supply, USB upstream	IVBAT		0.4	2.4	uA	Standby; typical @ 25oC, industrial MAX	41
Low Input Level	VIL	-0.3		0.8	V	IS type input buffer	44
High Input Level	VIH	2		3.6	V	IS type input buffer	44
Low Input Level	VIL	-0.3		0.4	V	I_RST type input buffer	44
High Input Level	VIH	1.25		3.6	V	I_RST type input buffer	44
Low Input Level	VIL	-0.3		0.35	V	I_SMB type input buffer	44
Low Output Level	VOL			0.4	V	O8 type buffers, IOL = 8 mA	44
Low Input Level (XTAL1/REFCLK)	VIL	-0.3		0.35	V	ICLK type buffer	44
High Input Level (XTAL1/REFCLK)	VIH	0.8		3.6	V	ICLK type buffer	44
Thermal resistance junction-to-ambient	JA		33		°C/W	0 m/s	43
Thermal resistance junction-to-ambient	JA		29		°C/W	1 m/s	43
Thermal resistance junction-to-ambient	JA		26		°C/W	2.5 m/s	43
Thermal resistance junction-to-board	JB		19		°C/W		43
Thermal resistance junction-to-top-of-package	JC		3.5		°C/W		43
Thermal resistance junction-to-bottom-of-case	JT		0.3		°C/W	0 m/s	43
Thermal resistance junction-to-board	JB		18		°C/W	0 m/s	43
Total Allowable PPM Budget		-350		350	ppm	Crystal, printed +/-350 PPM	47
Frequency	Ffund		24		MHz	Fundamental mode, parallel resonant crystal	47
Operating Temperature Range		-40		85	oC	Industrial version (Notes 9-1, 9-2)	47
Chip enable (SPI_CE_EN) high time	tceh	100			ns	SPI 30 MHz operation	46
Clock to input data	tclq			13	ns	SPI 30 MHz operation	46
Input data hold time	tdh	0			ns	SPI 30 MHz operation	46
Output setup time	tos	5			ns	SPI 30 MHz operation	46
Output hold time	toh	5			ns	SPI 30 MHz operation	46
Clock to output valid	tov			4	ns	SPI 30 MHz operation	46
Chip enable low to first clock	tcel			12	ns	SPI 30 MHz operation	46
Last clock to chip enable high	tceh			12	ns	SPI 30 MHz operation	46
Chip enable (SPI_CE_EN) high time	tceh	50			ns	SPI 60 MHz operation	46
Clock to input data	tclq			9	ns	SPI 60 MHz operation	46
RESET_N input assertion time	trstia	5			us	RESET_N configuration strap timing	45
Configuration strap hold after external power supplies at operational levels	tcsh	1			ms	Power-on configuration strap valid timing	45

CAD (KiCad official)

Symbol: USB4604I-1080HN
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: usb4604i-1080hn-etched.step / usb4604i-1080hn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb4604i-1080hn.step / usb4604i-1080hn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (55 pp, sha256 c71c99d8530091c2, retrieved 2026-11-09, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

USB4604I-1080HN

Verified USB4604I-1080HN

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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