USB4604-1080HN from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Battery power supply input; a 4.7 µF (<1 Ω ESR) capacitor to ground is required for internal 3.3V regulator stability.
2	NC	unconnected	No connect; must be left floating for normal device operation.
3	SWAP_USBDN1_DM/PRT_DIS_M1	bidirectional	Downstream USB Port 1 D- data signal (swappable with upstream Port 0); PRT_DIS_M1 and PRT_DIS_P1 must both be tied to VDD33 at reset to disable Port 1.
4	SWAP_USBDN1_DP/PRT_DIS_P1	bidirectional	Downstream USB Port 1 D+ data signal (swappable with upstream Port 0); PRT_DIS_P1 and PRT_DIS_M1 must both be tied to VDD33 at reset to disable Port 1.
5	USBDN2_DM/PRT_DIS_M2	bidirectional	Downstream USB Port 2 D- data signal; PRT_DIS_M2 and PRT_DIS_P2 must both be tied to VDD33 at reset to disable Port 2.
6	USBDN2_DP/PRT_DIS_P2	bidirectional	Downstream USB Port 2 D+ data signal; PRT_DIS_P2 and PRT_DIS_M2 must both be tied to VDD33 at reset to disable Port 2.
7	NC	unconnected	No connect; must be left floating for normal device operation.
8	USBDN3_DM/PRT_DIS_M3	bidirectional	Downstream USB Port 3 D- data signal; PRT_DIS_M3 and PRT_DIS_P3 must both be tied to VDD33 at reset to disable Port 3.
9	USBDN3_DP/PRT_DIS_P3	bidirectional	Downstream USB Port 3 D+ data signal; PRT_DIS_P3 and PRT_DIS_M3 must both be tied to VDD33 at reset to disable Port 3.
10	USBDN4_DM/PRT_DIS_M4	bidirectional	Downstream USB Port 4 D- data signal; PRT_DIS_M4 and PRT_DIS_P4 must both be tied to VDD33 at reset to disable Port 4.
11	USBDN4_DP/PRT_DIS_P4	bidirectional	Downstream USB Port 4 D+ data signal; PRT_DIS_P4 and PRT_DIS_M4 must both be tied to VDD33 at reset to disable Port 4.
12	VDDA33	power_in	+3.3V analog power supply; a 1.0 µF (<1 Ω ESR) capacitor to ground is required for regulator stability.
13	SOF	output	Outputs an 8 kHz clock synchronized with the USB Host SOF, controlled by the SOF_ENABLE bit in the UTIL_CONFIG1 register.
14	SUSPEND	output	Indicates the entire hub has entered USB suspend so VBUS current consumption should be reduced per the USB specification; must be enabled via the Protouch configuration tool.
15	PRTPWR1/PRTCTL1	bidirectional	Port 1 power enable output (0 = power disabled, 1 = power enabled); when configured as PRTCTL1 it also serves as the Port 1 over-current sense input OCS1_N.
16	OCS1_N	input	Active-low over-current sense input from an external current monitor indicating an over-current condition on USB Port 1; internal pull-up.
17	VDDCR12	power_in	+1.2V core power supply; in single-supply or dual-supply configurations where 1.2V is not used, a 1.0 µF (<1 Ω ESR) capacitor to ground is required for regulator stability.
18	VDD33	power_in	+3.3V power supply that must be connected to VDDA33.
19	PRTPWR2/PRTCTL2	bidirectional	Port 2 power enable output (0 = power disabled, 1 = power enabled); when configured as PRTCTL2 it also serves as the Port 2 over-current sense input OCS2_N.
20	OCS2_N	input	Active-low over-current sense input from an external current monitor indicating an over-current condition on USB Port 2; internal pull-up.
21	PRTPWR3/PRTCTL3	bidirectional	Port 3 power enable output (0 = power disabled, 1 = power enabled); when configured as PRTCTL3 it also serves as the Port 3 over-current sense input OCS3_N.
22	NC	unconnected	No connect; must be left floating for normal device operation.
23	NC	unconnected	No connect; must be left floating for normal device operation.
24	SPI_DI	input	SPI data input; internal pull-down enabled.
25	SPI_CE_N	output	Active-low SPI chip enable output; driven high in powerdown states if SPI is enabled.
26	SPI_DO/SPI_SPD_SEL	bidirectional	SPI data output (12 mA sink/source); the SPI_SPD_SEL configuration strap selects SPI speed at reset (0 = 30 MHz default, 1 = 60 MHz).
27	SPI_CLK	output	SPI clock output (12 mA sink/source).
28	UART_RX/OCS3_N	input	Internal UART receive input at 3.3V (RS232 operation requires an external 12V translator); also serves as active-low Port 3 over-current sense input OCS3_N.
29	PRTPWR4/PRTCTL4	bidirectional	Port 4 power enable output (0 = power disabled, 1 = power enabled); when configured as PRTCTL4 it also serves as the Port 4 over-current sense input OCS4_N.
30	UART_TX/OCS4_N	bidirectional	Internal UART transmit output at 3.3V (RS232 operation requires an external 12V driver); also serves as active-low Port 4 over-current sense input OCS4_N.
31	SDA/SMBDATA	bidirectional	I2C bidirectional serial data (open-drain, 8 mA sink); also serves as SMBus bidirectional serial data.
32	VDD33	power_in	+3.3V power supply that must be connected to VDDA33.
33	SCL/SMBCLK	input	I2C serial clock input; also serves as SMBus serial clock input.
34	NC	unconnected	No connect; must be left floating for normal device operation.
35	RESET_N	input	Active-low system reset input; the active-low pulse must be at least 5 µs wide.
36	VBUS_DET	input	Detects upstream bus power; on detachable hubs it must connect to upstream VBUS through a 50k/100k resistor divider to provide 3.3V.
37	VDDA33	power_in	+3.3V analog power supply; a 1.0 µF (<1 Ω ESR) capacitor to ground is required for regulator stability.
38	VDD12	power_in	+1.2V HSIC power supply input; for HSIC operation it must be tied to VDDCR12.
39	FLEX_HSIC_UP_STROBE	bidirectional	Upstream HSIC Port 0 STROBE signal (can be optionally swapped with downstream Port 1 signals).
40	FLEX_USBUP_DM/PRT_DIS_M0	bidirectional	Upstream USB Port 0 D- data signal (can be optionally swapped with downstream Port 1); PRT_DIS_M0 and PRT_DIS_P0 must both be tied to VDD33 at reset to place Port 0 into HSIC mode.
41	FLEX_USBUP_DP/PRT_DIS_P0	bidirectional	Upstream USB Port 0 D+ data signal (can be optionally swapped with downstream Port 1); PRT_DIS_P0 and PRT_DIS_M0 must both be tied to VDD33 at reset to place Port 0 into HSIC mode.
42	FLEX_HSIC_UP_DATA	bidirectional	Upstream HSIC Port 0 DATA signal (can be optionally swapped with downstream Port 1 signals).
43	XTAL2	output	External 24 MHz crystal output; should be left unconnected when XTAL1/REFCLK is driven by a single-ended clock oscillator.
44	XTAL1/REFCLK	input	External 24 MHz crystal input, or reference clock input that may be driven by a single-ended clock oscillator.
45	NC	unconnected	No connect; must be left floating for normal device operation.
46	RBIAS	passive	A 12.0k (+/- 1%) resistor attached from ground to this pin sets the transceiver's internal bias settings.
47	VDDCOREREG	power_in	+1.8-3.3V core power supply input to the internal +1.2V regulator; may be tied to VDD33 for single-supply operation when VBAT equals +3.3V.
48	VDDA33	power_in	+3.3V analog power supply; a 1.0 µF (<1 Ω ESR) capacitor to ground is required for regulator stability.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-48-EP(7x7)
Category	Communication Interface Chip/UART/485/232
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VBAT Supply Voltage		0		5.5	V	Note 9-1	39
VDDCOREREG Supply Voltage		0		3.6	V	Note 9-1	39
Positive voltage on input signal pins, with respect to ground				3.6	V	Note 9-2	39
Negative voltage on input signal pins, with respect to ground		-0.5			V	Note 9-3	39
Positive voltage on USB DP/DM signals, with respect to ground				5.5	V	Note 9-4	39
Storage Temperature		-55		150	°C		39
VBAT Supply Voltage		3		5.5	V		40
VDDCOREREG Supply Voltage		1.6		2	V	Note 9-5: connected to external +1.8V power supply	40
VDDCOREREG Supply Voltage		3		3.6	V	Note 9-5: connected to VDD33	40
Power Supply Rise Time (tRT)	tRT(max)			10	mS	Note 9-6: RESET_N asserted at power-on	40
Power Supply Rise Time (tRT)	tRT(max)			1	mS	Note 9-6: RESET_N not used at power-on (tied high)	40
Ambient Operating Temperature in Still Air (TA)	TA	0		70	°C	Note 9-7: commercial version	40
Operational/unconfigured current, USB upstream: HS host / 1 HS device			30	40	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 1 HS device			40	45	mA	USB upstream; VDDCOREREG supply column	41
Operational/unconfigured current, USB upstream: HS host / 2 HS devices			55	65	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 2 HS devices			50	55	mA	USB upstream; VDDCOREREG supply column	41
Operational/unconfigured current, USB upstream: HS host / 4 HS devices			100	105	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 4 HS devices			65	75	mA	USB upstream; VDDCOREREG supply column	41
Operational/unconfigured current, USB upstream: HS host / 1 FS device			20	25	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 1 FS device			30	40	mA	USB upstream; VDDCOREREG supply column	41
Operational/unconfigured current, USB upstream: HS host / 2 FS devices			20	30	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 2 FS devices			40	40	mA	USB upstream; VDDCOREREG supply column	41
Operational/unconfigured current, USB upstream: HS host / 4 FS devices			25	30	mA	USB upstream; VBAT supply column	41
Operational/unconfigured current, USB upstream: HS host / 4 FS devices			40	45	mA	USB upstream; VDDCOREREG supply column	41
Single supply suspend current	IVBAT		320	1200	uA	USB upstream; typical @ 25oC; max = Commercial MAX	41
Single supply standby current	IVBAT		0.4	2	uA	USB upstream; typical @ 25oC; max = Commercial MAX	41
IS Type Input Buffer Low Input Level	VIL	-0.3		0.8	V		44
IS Type Input Buffer High Input Level	VIH	2		3.6	V		44
I_RST Type Input Buffer Low Input Level	VIL	-0.3		0.4	V		44
I_RST Type Input Buffer High Input Level	VIH	1.25		3.6	V		44
I_SMB Type Input Buffer Low Input Level	VIL	-0.3		0.35	V		44
I_SMB Type Input Buffer High Input Level	VIH	1.25		3.6	V		44
O8 Type Buffers Low Output Level	VOL			0.4	V	IOL = 8 mA	44
OD8 Type Buffer Low Output Level	VOL			0.4	V	IOL = 8 mA	44
O12 Type Buffers Low Output Level	VOL			0.4	V	IOL = 12 mA	44
OD12 Type Buffer Low Output Level	VOL			0.4	V	IOL = 12 mA	44
ICLK Type Buffer (XTAL1/REFCLK Input) Low Input Level	VIL	-0.3		0.8	V		44
ICLK Type Buffer (XTAL1/REFCLK Input) High Input Level	VIH	0.35		3.6	V		44
Crystal Total Allowable PPM Budget		-350		350	PPM		47
Crystal Operating Temperature Range		0		70	°C	Notes 9-1, 9-2: commercial version	47
Crystal Frequency (fundamental)	Ffund		24		MHz	Fundamental mode, parallel resonant	47
Junction-to-ambient thermal resistance (JA) at 0 m/s	JA		33		°C/W	Velocity 0 m/s	43
Junction-to-ambient thermal resistance (JA) at 1 m/s	JA		29		°C/W	Velocity 1 m/s	43
Junction-to-ambient thermal resistance (JA) at 2.5 m/s	JA		26		°C/W	Velocity 2.5 m/s	43
Junction-to-board thermal resistance	JB		19		°C/W		43
Junction-to-top-of-package thermal resistance	JC		3.5		°C/W		43
Junction-to-bottom-of-case thermal resistance	JT		0.3		°C/W	Velocity 0 m/s	43
Junction-to-board thermal resistance (second JB row)	JB		18		°C/W	Velocity 0 m/s	43

CAD (KiCad official)

Symbol: USB4604-1080HN
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: usb4604-1080hn-etched.step / usb4604-1080hn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb4604-1080hn.step / usb4604-1080hn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (55 pp, sha256 c71c99d8530091c2, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

USB4604-1080HN

Verified USB4604-1080HN

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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