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USB3503T-I

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Microchip Tech USB ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232usb3503t-ifactory-2.0.0extractor-text

Verified USB3503T-I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: USB3503T-I · QFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 74-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-8k7xb0w2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ usb3503t-i.kicad_sym✓ usb3503t-i.kicad_mod✓ usb3503t-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers usb3503t-i: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
usb3503t-i-etched.glb Publish 0.1.0 · Ray 1d ago
usb3503t-i-etched.step usb3503t-i: factory component page (tier=mfr) · Ray 1d ago
usb3503t-i-hero.glb usb3503t-i: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
usb3503t-i-hero.overlay.json Publish 0.1.0 · Ray 1d ago
usb3503t-i.glb Publish 0.1.0 · Ray 1d ago
usb3503t-i.kicad_mod Publish 0.1.0 · Ray 1d ago
usb3503t-i.kicad_sym Publish 0.1.0 · Ray 1d ago
usb3503t-i.lbr Publish 0.1.0 · Ray 1d ago
usb3503t-i.step Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray 1d ago

USB3503T-I

Microchip Tech · USB ICs · QFN-32-EP(5x5)

USB3503T-I from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OCS_N input Over Current Sense input from an external current monitor for port 3 or a ganged supply; negated high = no fault, asserted low = over-current fault reported.
2 HUB_CONNECT input Hub moves to the Hub Communication Stage when this pin is asserted high; tie to ground to wait for the connect_n bit, tie to VDD33_BYP for automatic transition, or drive low-to-high, and never drive high in Standby Mode.
3 NC unconnected No connect.
4 PRTPWR output Open-drain port power control output for port 3 or a ganged supply; asserted high = external device should provide power, negated low = external device should disable power.
5 INT_N output Open-drain active-low interrupt whose function is set by CFGP.INTSUSP (general interrupt or USB suspend indication); also sampled during Hub.Init to select primary (high) or secondary (low) REFCLK frequencies, and tied to VDD33_BYP if unused.
6 VDD12_BYP power_out 1.2 V regulator output requiring a 1.0 uF (<1 ohm ESR) capacitor to ground placed as close as possible to the device.
7 SDA bidirectional I2C serial data, open-drain I/O.
8 SCL input I2C serial clock input.
9 REF_SEL1 input Reference clock select 1, tied to ground or VDD33_BYP to match the REFCLK frequency per Table 3-3/3-4 and latched during Hub.Init.
10 REF_SEL0 input Reference clock select 0, tied to ground or VDD33_BYP to match the REFCLK frequency per Table 3-3/3-4 and latched during Hub.Init.
11 VDD12_BYP power_out 1.2 V regulator output requiring a 1.0 uF (<1 ohm ESR) capacitor to ground placed as close as possible to the device.
12 RESET_N input Active-low reset that resets the chip and holds it in low power STANDBY MODE.
13 VDD12_BYP power_out 1.2 V regulator output requiring a 1.0 uF (<1 ohm ESR) capacitor to ground placed as close as possible to the device.
14 NC unconnected No connect.
15 DATA bidirectional Upstream HSIC DATA pin of the hub.
16 STROBE bidirectional Upstream HSIC STROBE pin of the hub.
17 NC unconnected No connect.
18 NC unconnected No connect.
19 USBDN3_DM bidirectional USB downstream port 3 D- data pin; there is no port disable strap option on this port.
20 USBDN3_DP bidirectional USB downstream port 3 D+ data pin; there is no port disable strap option on this port.
21 USBDN2_DM bidirectional USB downstream port 2 D- data pin; sampled at RESET_N negation and tied with D+ to VDD33_BYP to disable the port.
22 USBDN2_DP bidirectional USB downstream port 2 D+ data pin; sampled at RESET_N negation and tied with D- to VDD33_BYP to disable the port.
23 USBDN1_DM bidirectional USB downstream port 1 D- data pin; sampled at RESET_N negation and tied with D+ to VDD33_BYP to disable the port.
24 USBDN1_DP bidirectional USB downstream port 1 D+ data pin; sampled at RESET_N negation and tied with D- to VDD33_BYP to disable the port.
25 VBAT power_in Battery power supply input; see Section 9.0 for power supply configuration options.
26 VDD33_BYP power_out 3.3 V regulator output requiring a 4.7 uF (<1 ohm ESR) capacitor to ground placed as close as possible to the device.
27 NC unconnected No connect.
28 VDD_CORE_REG power_in Power supply input to the 1.2 V regulator for the digital core; connect to VDD33_BYP for single supply applications.
29 REFCLK input Reference clock input driven with a square wave from 0 V to VDD33_BYP, using only the positive edge, with peak-to-peak jitter under 1 ns over 10 s.
30 RBIAS passive Analog pin for a 12.0 kohm (+/-1%) resistor to ground that sets the USB transceiver internal bias.
31 NC unconnected No connect.
32 VDD33_BYP power_out 3.3 V regulator output requiring a 4.7 uF (<1 ohm ESR) capacitor to ground placed as close as possible to the device.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VBAT absolute max VBAT -0.5 5.5 V 51
VDD_CORE_REG absolute max VDD_CORE_REG -0.5 4.6 V 51
VDD33 absolute max VDD33_BYP -0.5 4.6 V 51
Maximum IO Voltage to Ground VIO -0.5 4.6 V 51
REFCLK Voltage VMAX_REFCLK -0.5 3.6 V 51
Voltage on USB+ and USB- pins VMAX_USB -0.5 5.5 V 51
Operating Temperature (Industrial) TMAX_OP -40 85 °C Industrial 51
Storage Temperature TMAX_STG -55 150 °C 51
Junction Temperature TJMAX 125 °C 51
VBAT supply VBAT 2.9 5.5 V 51
VDD_CORE_REG (external supply) VDD_CORE_REG 1.6 1.8 2 V Note 10-1 51
VDD_CORE_REG (tied to VDD33_BYP) VDD_CORE_REG 3 3.3 3.6 V Note 10-2 51
Input Voltage (DP, DM) VIUSB -0.3 5.5 V 51
Input Voltage (STROBE, DATA) VIHSIC -0.3 1.2 1.32 V 51
Input Voltage on I/O Pins VI -0.3 1.8 3.6 V 51
Voltage on REFCLK VREFCLK -0.3 3.6 V 51
Ambient Temperature (Industrial) TA -40 85 °C Industrial 51
Thermal resistance junction to ambient, 32-pin SQFN 44 °C/W Measured in still air 52
Thermal resistance junction to bottom of case, 32-pin SQFN 0.6 °C/W Measured in still air 52
Thermal resistance junction to top of case, 32-pin SQFN 6.3 °C/W 52
Operating current VBAT, HS, 3 ports active (dual supply) IVBAT(HS) 55 65 68 mA Active USB Transfer, RESET_N = 1, 3 Downstream Ports Active 52
Standby current VBAT, industrial (dual supply) IVBAT(STDBY) 0 0.6 3.9 µA RESET_N = 0, Industrial Temp 53
Standby current core, industrial (dual supply) ICORE(STDBY) 0 0 0.9 µA RESET_N = 0, Industrial Temp 53
Suspend current VBAT, industrial (dual supply) IVBAT(SPND) 65 73 125 µA USB Suspend, Industrial Temp 53
Suspend current core, industrial (dual supply) ICORE(SPND) 125 165 1050 µA USB Suspend, Industrial Temp 53
Operating current VBAT, HS, 3 ports active (single supply) IVBAT(HS) 88 98 110 mA Active USB Transfer, RESET_N = 1, 3 Downstream Ports Active 53
Standby current VBAT, industrial (single supply) IVBAT(STDBY) 0 0.6 3.1 µA RESET_N = 0, Industrial Temp 53
Low-Level Input Voltage (I2C pullups < 2.1V) VIL -0.3 0.42 V Note 10-1 54
Low-Level Input Voltage (I2C pullups > 2.1V) VIL -0.3 0.34 V Note 10-2 54
High-Level Input Voltage VIH 1.25 V Upper limit VDD33_BYP+0.3V 54
Low-Level Input Voltage RESET VIL_RST -0.3 0.38 V 54
High-Level Input Voltage RESET VIH_RST 1 V Upper limit VDD33_BYP+0.3V 54
Low-Level Input Voltage OSC VIL_OSC -0.3 0.55 V 54
High-Level Input Voltage OSC VIH_OSC 0.8 V Upper limit VDD33_BYP+0.3V 54
Low-Level Input Voltage REFCLK VIL_REF -0.3 0.5 V 54
High-Level Input Voltage REFCLK VIH_REF 1.4 V Upper limit VDD33_BYP+0.3V 54
Clock Input Capacitance REFCLK CIN 2 pF 54
Low-Level Output Voltage VOL 0.4 V @ IOL=12mA sink current 54
Pin Capacitance Cpin 2 20 pF 54
Output Current Capability IO 12 20 24 mA 54
Differential Receiver Input Sensitivity VDIFS 0.2 V / V(DP) - V(DM) / 55
Differential Receiver Common-Mode Voltage VCMFS 0.8 2.5 V 55
Single-Ended Receiver Low Level Input Voltage VILSE 0.8 V 55
Single-Ended Receiver High Level Input Voltage VIHSE 2 V 55
Low Level Output Voltage VFSOL 0.3 V Pull-up resistor on DP; RL = 1.5kΩ to VDD33_BYP 55
High Level Output Voltage VFSOH 2.8 3.6 V Pull-down resistor on DP, DM; RL = 15kΩ to GND 55
Driver Output Impedance for HS ZHSDRV 40.5 45 49.5 Ω Steady state drive 55
Input Impedance ZINP 1 MΩ RX, RPU, RPD disabled 55
Pull-dn Resistor Impedance RPD 14.25 16.9 20 kΩ Note 10-3 55
HS Differential Input Sensitivity VDIHS 100 mV / V(DP) - V(DM) / 55
HS Squelch Detection Threshold (Differential) VHSSQ 100 150 mV 55
HS Disconnect Threshold VHSDSC 525 625 mV 55
HS High Level Output Voltage VHSOH 360 440 mV 45Ω load 55
OFF-State Leakage Current ILZ -10 10 µA 55
Regulator Output Voltage VDD33 VDD33 2.8 3.3 3.6 V 5.5V > VBAT > 2.9V 56
Regulator Output Voltage VDD12 VDD12 1.1 1.2 1.3 V 3.6V > VDD33 > 2.8V 56
Minimum Active Low Pulse on RESET_N TRESET 1 ms RESET_N = '0' 56
Hub Configuration Time-out THUBCONFIG 94 95 96 ms 18

CAD (KiCad official)

  • Symbol: USB3503T-I
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: usb3503t-i-etched.step / usb3503t-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb3503t-i.step / usb3503t-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (74 pp, sha256 262b302459ecd7f2, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF