component
USB3370B-EZK-TR
Public Made by Adomby adom
Microchip Tech Receivers & Transceivers, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownUSB3370B-EZK-TR
Microchip Tech · Receivers & Transceivers · QFN-32-EP(5x5)
USB3370B-EZK-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DATA[0] | bidirectional | ULPI bidirectional data bus bit 0 (LSB), CMOS I/O; in UART mode it carries TXD to the DM pin. |
| 2 | VDDIO | power_in | ULPI interface supply voltage, specified at 1.8V to 3.3V. |
| 3 | RBIAS | passive | Bias resistor pin requiring a 10kΩ (±1%) resistor to ground placed as close as possible to the device, with nominal voltage of 0.8V during ULPI operation. |
| 4 | DM | bidirectional | D- pin of the USB cable, an analog I/O. |
| 5 | DP | bidirectional | D+ pin of the USB cable, an analog I/O. |
| 6 | EXTVBUS | input | External Vbus detect input, tolerant to 0 to 5.0V, connected to the fault output of an external USB power switch or Vbus Valid comparator and internally pulled down. |
| 7 | ID | input | USB ID input, connected to VDD33 for device, grounded for host, and to the USB connector for OTG applications. |
| 8 | GND | power_in | Ground pin for the device. |
| 9 | NC | unconnected | No connect; leave pin floating. |
| 10 | NC | unconnected | No connect; leave pin floating. |
| 11 | VBAT | power_in | Regulator input supplied from 3.0V to 5.5V that feeds the integrated 3.3V LDO and must never be connected to VDD33. |
| 12 | CPEN_N | output | Open-drain external 5V supply enable output, active low, tri-stated on power-on reset and tolerant to 5.5V maximum. |
| 13 | VBUS | power_in | Analog pin for VBUS comparator inputs and VBUS pulsing during session request, requiring an external resistor RVBUS to the USB connector and tolerant to 30V with that resistor. |
| 14 | VDD33 | power_out | 3.3V regulator output requiring a 1.0uF (<1 ohm ESR) bypass capacitor to ground placed close to the device, with 3.0V to 3.6V range. |
| 15 | REFCLK | input | Reference clock or XI crystal input in ULPI Clock Output mode, and 60MHz ULPI clock input in ULPI Clock Input mode, accepting 0 to 3.6V drive. |
| 16 | XO | output | Crystal output pin that should be left floating when an external clock is applied on XI. |
| 17 | RESETB | input | Active-low reset and suspend input that disables both regulators when low and resets the ULPI registers when asserted for at least 1 microsecond. |
| 18 | VDD18 | power_out | 1.8V regulator output requiring a 1.0uF (<1 ohm ESR) bypass capacitor to ground placed close to the device, with 1.6V to 2.0V range. |
| 19 | DIR | output | Data bus direction output; driven high when the PHY has data for the Link and low when it monitors the bus for commands. |
| 20 | STP | input | Active-high stop input asserted by the Link for one clock cycle to stop the current data stream on the bus. |
| 21 | NXT | output | Active-high next output asserted by the PHY to throttle data, indicating when the current byte has been accepted. |
| 22 | VDDIO | power_in | ULPI interface supply voltage, specified at 1.8V to 3.3V. |
| 23 | DATA[7] | bidirectional | ULPI bidirectional data bus bit 7 (MSB), CMOS I/O. |
| 24 | DATA[6] | bidirectional | ULPI bidirectional data bus bit 6, CMOS I/O. |
| 25 | DATA[5] | bidirectional | ULPI bidirectional data bus bit 5, CMOS I/O. |
| 26 | DATA[4] | bidirectional | ULPI bidirectional data bus bit 4, CMOS I/O. |
| 27 | CLKOUT | output | 60MHz ULPI clock output in ULPI Clock Output mode, driven synchronous to all ULPI signals, and connected to VDDIO to select ULPI Clock Input mode. |
| 28 | DATA[3] | bidirectional | ULPI bidirectional data bus bit 3, CMOS I/O. |
| 29 | NC | unconnected | No connect; leave pin floating. |
| 30 | VDDIO | power_in | ULPI interface supply voltage, specified at 1.8V to 3.3V. |
| 31 | DATA[2] | bidirectional | ULPI bidirectional data bus bit 2, CMOS I/O. |
| 32 | DATA[1] | bidirectional | ULPI bidirectional data bus bit 1, CMOS I/O. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Logic ICs |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum VBUS, VBAT and ID voltage to GND | VMAX_USB | -0.5 | 6 | V | Voltage measured at pin. VBUS tolerant to 30V with external RVBUS. | 9 | |
| DP and DM voltage to GND | VMAX_DPDM | -0.5 | 5 | V | 9 | ||
| Maximum VDD18 voltage to Ground | VMAX_18V | -0.5 | 2.5 | V | 9 | ||
| Maximum VDD33 voltage to Ground | VMAX_33V | -0.5 | 4 | V | 9 | ||
| Maximum VDDIO voltage to Ground | VMAX_IOV | -0.5 | 4 | V | 9 | ||
| Maximum I/O voltage to Ground (EXTVBUS, CPEN_N) | VMAX_IN | -0.5 | 5.5 | V | 9 | ||
| Operating Temperature | TMAX_OP | -40 | 85 | C | 9 | ||
| Storage Temperature | TMAX_STG | -55 | 150 | C | 9 | ||
| Junction Temperature | Tj | 125 | C | 9 | |||
| VBAT to GND | VBAT | 3 | 5.5 | V | 9 | ||
| VDD33 to GND | VDD33 | 3 | 3.3 | 3.6 | V | 9 | |
| VDD18 to GND | VDD18 | 1.6 | 1.8 | 2 | V | 9 | |
| VDDIO to GND | VDDIO | 1.6 | 3.6 | V | 9 | ||
| Input Voltage on Digital Pins (RESETB, STP, DIR, NXT, DATA[7:0]) | VI | 0 | V | 9 | |||
| Input Voltage on Digital Pins (EXTVBUS, CPEN_N) | VI | 0 | 5 | V | 9 | ||
| Voltage on Analog I/O Pins (DP, DM, ID) | VI(I/O) | 0 | V | 9 | |||
| VBUS to GND | VVMAX | 0 | 5.5 | V | 9 | ||
| Ambient Temperature | TA | -40 | 85 | C | 9 | ||
| Synchronous Mode Current (Default Configuration) | IVBAT(SYNC) | 24 | 27 | 29 | mA | USB Idle | 10 |
| Synchronous Mode Current (Default Configuration) | IVIO(SYNC) | 2 | 3 | 7 | mA | 10 | |
| Synchronous Mode Current (HS USB operation) | IVBAT(HS) | 33 | 35 | 37 | mA | Active USB Transfer | 10 |
| Synchronous Mode Current (HS USB operation) | IVIO(HS) | 5 | 6 | 14 | mA | 10 | |
| Synchronous Mode Current (FS/LS USB operation) | IVBAT(FS) | 25 | 28.5 | 30 | mA | Active USB Transfer | 10 |
| Synchronous Mode Current (FS/LS USB operation) | IVIO(FS) | 4 | 5 | 13 | mA | 10 | |
| Low Power Mode current | IVBAT(SUSPEND) | 29 | 32 | 83 | uA | VVBAT = 4.2V; VVDDIO = 1.8V | 10 |
| Low Power Mode current | IVIO(SUSPEND) | 0 | 0 | 2 | uA | 10 | |
| RESET Mode current | IVBAT(RSTB) | 0.1 | 1 | 12 | uA | RESETB = 0; VVBAT = 4.2V; VVDDIO = 1.8V | 10 |
| RESET Mode current | IVIO(RSTB) | 0 | 0 | 7 | uA | 10 | |
| Suspend Recovery Time | TSTART | 1 | 1.1 | 1.32 | ms | LPM Enable = 0 | 10 |
| PHY Preparation Time (60MHz REFCLK) | TPREP | 1 | 1.1 | 1.32 | ms | LPM Enable = 0 | 10 |
| CLKOUT Duty Cycle | DCCLKOUT | 45 | 55 | % | ULPI Clock Input Mode | 10 | |
| REFCLK Duty Cycle | DCREFCLK | 20 | 80 | % | 10 | ||
| REFCLK Frequency Accuracy | FREFCLK | -500 | 500 | PPM | 10 | ||
| Setup time (STP, data in), model-specific REFCLK | TSC, TSD | 5 | ns | Model-specific REFCLK | 11 | ||
| Hold time (STP, data in), model-specific REFCLK | THC, THD | 0 | ns | Model-specific REFCLK | 11 | ||
| Output delay (control out, 8-bit data out), model-specific REFCLK | TDC, TDD | 1.5 | 6 | ns | Model-specific REFCLK | 11 | |
| Setup time (STP, data in), 60MHz REFCLK | TSC, TSD | 3 | ns | 60MHz REFCLK | 11 | ||
| Hold time (STP, data in), 60MHz REFCLK | THC, THD | 0 | ns | 60MHz REFCLK | 11 | ||
| Output delay (control out, 8-bit data out), 60MHz REFCLK | TDC, TDD | 0.5 | 6 | ns | 60MHz REFCLK | 11 | |
| Low-Level Input Voltage | VIL | 0.8 | V | 11 | |||
| Low-Level Output Voltage | VOL | 0.4 | V | IOL = 8mA | 11 | ||
| STP pull-up resistance | RSTP | 55 | 67 | 80 | kΩ | InterfaceProtectDisable = 0 | 11 |
| DATA[7:0] pull-down resistance | RDATA_PD | 55 | 67 | 77 | kΩ | ULPI Synchronous Mode | 11 |
| Differential Receiver Common-Mode Voltage | VCMFS | 0.8 | 2.5 | V | 12 | ||
| Single-Ended Receiver Low Level Input Voltage | VILSE | 0.8 | V | Note 4-8 | 12 | ||
| Single-Ended Receiver High Level Input Voltage | VIHSE | 2 | V | Note 4-8 | 12 | ||
| Low Level Output Voltage | VFSOL | 0.3 | V | Pull-up resistor on DP; RL = 1.5kΩ to VDD33 | 12 | ||
| High Level Output Voltage | VFSOH | 2.8 | 3.6 | V | Pull-down resistor on DP, DM; RL = 15kΩ to GND; Note 4-8 | 12 | |
| Driver Output Impedance for HS | ZHSDRV | 40.5 | 45 | 49.5 | Ω | Steady state drive | 12 |
| Pull-up Resistor Impedance RPU (Bus Idle) | RPU | 0.9 | 1.24 | 1.575 | kΩ | Bus Idle, Note 4-7 | 12 |
| Pull-dn Resistor Impedance | RPD | 14.25 | 16.9 | 20 | kΩ | Note 4-7 | 12 |
| HS Squelch Detection Threshold (Differential) | VHSSQ | 100 | 150 | mV | VariSense[1:0] = 00b; Note 4-9 | 12 | |
| HS Disconnect Threshold | VHSDSC | 525 | 625 | mV | 12 | ||
| High Speed High Level Output Voltage (DP/DM referenced to GND) | VHSOH | 360 | 440 | mV | 45Ω load | 12 | |
| Chirp-J Output Voltage (Differential) | VCHIRPJ | 700 | 1100 | mV | HS termination resistor disabled, pull-up resistor connected. 45Ω load. | 12 | |
| Transceiver Input Capacitance | CIN | 5 | 10 | pF | Pin to GND | 13 | |
| Differential Receiver Common-Mode Voltage | VSessVld | 0.8 | 1.4 | 2 | V | SessVld trip point | 14 |
| VbusVld trip point | VVbusVld | 4.4 | 4.58 | 4.75 | V | 14 | |
| VBUS Pull-Up | RVPU | 1.29 | 1.34 | 1.45 | kΩ | VBUS to VDD33; Note 4-10 (ChargeVbus = 1) | 14 |
| VBUS Pull-down | RVPD | 1.55 | 1.7 | 1.85 | kΩ | VBUS to GND; Note 4-10 (DisChargeVbus = 1) | 14 |
CAD (KiCad official)
- Symbol:
USB3370B-EZK-TR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
usb3370b-ezk-tr-etched.step/usb3370b-ezk-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb3370b-ezk-tr.step/usb3370b-ezk-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (75 pp, sha256
df0f7f83b17ead20, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).