component
USB2514BT
Public Made by Adomby adom
Microchip Tech USB ICs, QFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUSB2514BT
Microchip Tech · USB ICs · QFN-36-EP(6x6)
USB2514BT from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USBDM_DN1/PRT_DIS_M1 | bidirectional | Downstream port 1 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation (pull up both PRT_DIS_M1 and PRT_DIS_P1 to disable the port). |
| 2 | USBDP_DN1/PRT_DIS_P1 | bidirectional | Downstream port 1 hi-speed USB D+ data, also the port-disable strap; use a 10 k pull-up to 3.3 V to disable the port. |
| 3 | USBDM_DN2/PRT_DIS_M2 | bidirectional | Downstream port 2 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation. |
| 4 | USBDP_DN2/PRT_DIS_P2 | bidirectional | Downstream port 2 hi-speed USB D+ data, also the port-disable strap; use a 10 k pull-up to 3.3 V to disable the port. |
| 5 | VDDA33 | power_in | 3.3 V analog power. |
| 6 | USBDM_DN3/PRT_DIS_M3 | bidirectional | Downstream port 3 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation. |
| 7 | USBDP_DN3/PRT_DIS_P3 | bidirectional | Downstream port 3 hi-speed USB D+ data, also the port-disable strap; use a 10 k pull-up to 3.3 V to disable the port. |
| 8 | USBDM_DN4/PRT_DIS_M4 | bidirectional | Downstream port 4 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation. |
| 9 | USBDP_DN4/PRT_DIS_P4 | bidirectional | Downstream port 4 hi-speed USB D+ data, also the port-disable strap; use a 10 k pull-up to 3.3 V to disable the port. |
| 10 | VDDA33 | power_in | 3.3 V analog power. |
| 11 | TEST | input | Test pin with internal pull-down: treat as no connect or connect to ground; no trace or signal should be routed to it. |
| 12 | PRTPWR1/BC_EN1 | bidirectional | Port 1 USB power enable output, also battery-charging strap (internal pull-down, 1 = battery charging supported) sampled at RESET_N negation. |
| 13 | OCS_N1 | input | Over-current sense input for port 1 from an external current monitor, with internal pull-up. |
| 14 | CRFILT | passive | Core regulator filter: up to a 0.1 uF low-ESR capacitor to VSS, or left unconnected. |
| 15 | VDD33 | power_in | 3.3 V digital power. |
| 16 | PRTPWR2/BC_EN2 | bidirectional | Port 2 USB power enable output, also battery-charging strap (internal pull-down) sampled at RESET_N negation. |
| 17 | OCS_N2 | input | Over-current sense input for port 2 from an external current monitor, with internal pull-up. |
| 18 | PRTPWR3/BC_EN3 | bidirectional | Port 3 USB power enable output, also battery-charging strap (internal pull-down) sampled at RESET_N negation. |
| 19 | OCS_N3 | input | Over-current sense input for port 3 from an external current monitor, with internal pull-up. |
| 20 | PRTPWR4/BC_EN4 | bidirectional | Port 4 USB power enable output, also battery-charging strap (internal pull-down) sampled at RESET_N negation. |
| 21 | OCS_N4 | input | Over-current sense input for port 4 from an external current monitor, with internal pull-up. |
| 22 | SDA/SMBDATA/NON_REM1 | bidirectional | Serial data (I2C) or SMBus data signal, also the non-removable port strap bit 1 sampled at RESET_N negation (47-100 k strap resistor). |
| 23 | VDD33 | power_in | 3.3 V digital power. |
| 24 | SCL/SMBCLK/CFG_SEL0 | bidirectional | Serial clock (I2C) or SMBus clock, also configuration select 0 latched at RESET_N negation to choose the configuration method. |
| 25 | HS_IND/CFG_SEL1 | bidirectional | Hi-speed upstream port indicator (asserted when connected at HS), also configuration select 1 latched at RESET_N negation. |
| 26 | RESET_N | input | Active-low reset input; minimum active low pulse is 1 us. |
| 27 | VBUS_DET | input | Detects upstream VBUS power to decide when to assert the internal D+ pull-up; connect to VBUS via a 2:1 divider (two 100 k suggested) or to a host control output or the host 3.3 V domain when self-powered. |
| 28 | SUSP_IND/LOCAL_PWR/NON_REM0 | bidirectional | Active/suspend status LED output, local self-power detect input (high = local power available), and non-removable strap bit 0 sampled at RESET_N negation. |
| 29 | VDDA33 | power_in | 3.3 V analog power. |
| 30 | USBDM_UP | bidirectional | Upstream USB D- data; connect to the upstream host, port or hub data signal. |
| 31 | USBDP_UP | bidirectional | Upstream USB D+ data; connect to the upstream host, port or hub data signal. |
| 32 | XTALOUT | output | Crystal output with 1.2 V p-p and weak (<1 mA) drive; leave unconnected when an external clock drives XTALIN/CLKIN. |
| 33 | XTALIN/CLKIN | input | 24 MHz crystal terminal or external 24 MHz clock input when no crystal is used. |
| 34 | PLLFILT | passive | PLL regulator filter: up to a 0.1 uF low-ESR capacitor to VSS, or left unconnected. |
| 35 | RBIAS | input | USB transceiver bias: a 12.0 k (+/-1%) resistor from this pin to ground. |
| 36 | VDDA33 | power_in | 3.3 V analog power. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36-EP(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 37 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TSTOR | -55 | 150 | °C | 39 | ||
| 3.3 V supply voltage | VDD33, VDDA33 | 4.6 | V | Applies to all packages | 39 | ||
| Voltage on any I/O pin | -0.5 | 5.5 | V | 39 | |||
| Voltage on XTALIN | -0.5 | 4 | V | 39 | |||
| Voltage on XTALOUT | -0.5 | 2.5 | V | 39 | |||
| Extended Commercial Operating Temperature | TAE | 0 | 85 | °C | Ambient temperature in still air | 39 | |
| 3.3 V supply voltage | VDD33, VDDA33 | 3 | 3.6 | V | Applies to all parts | 39 | |
| 3.3 V supply rise time | tRT33 | 0 | 400 | µs | See Figure 6-1 and Note 6-2 | 39 | |
| Voltage on any I/O pin | -0.3 | 5.5 | V | If any 3.3 V supply voltage drops below 3.0 V, MAX becomes (3.3 V supply voltage) + 0.5 | 39 | ||
| Voltage on XTALIN | -0.3 | 3.6 | V | Max printed as VDD33 | 39 | ||
| Low Input Level (I, IS) | VILI | 0.8 | V | TTL Levels | 40 | ||
| High Input Level (I, IS) | VIHI | 2 | V | TTL Levels | 40 | ||
| Input Leakage (I, IS) | IIL | -10 | 10 | µA | VIN = 0 to VDD33 | 40 | |
| Hysteresis (IS only) | VHYSI | 250 | 350 | mV | 40 | ||
| Low Input Leakage (IPU) | IILL | 35 | 90 | µA | VIN = 0 | 40 | |
| High Input Leakage (IPU) | IIHL | -10 | 10 | µA | VIN = VDD33 | 40 | |
| Low Input Leakage (IPD) | IILL | -10 | 10 | µA | VIN = 0 | 40 | |
| High Input Leakage (IPD) | IIHL | -90 | -35 | µA | VIN = VDD33 | 40 | |
| ICLK Low Input Level | VILCK | 0.3 | V | 40 | |||
| ICLK High Input Level | VIHCK | 0.9 | V | 40 | |||
| ICLK Input Leakage | IIL | -10 | 10 | µA | VIN = 0 to VDD33 | 40 | |
| Low Output Level (O12) | VOL | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 41 | ||
| High Output Level (O12) | VOH | 2.4 | V | IOH = -12 mA @ VDD33 = 3.3 V | 41 | ||
| Output Leakage | IOL | -10 | 10 | µA | 41 | ||
| Hysteresis (SD pad only) | IHYSC | 250 | 350 | mV | VIN = VDD33 (Note 6-1) | 41 | |
| Supply current unconfigured, Hi-Speed host, USB2514B | ICCINTHS | 45 | 50 | mA | 41 | ||
| Supply current unconfigured, Full-Speed host, USB2514B | ICCINTFS | 35 | 40 | mA | 41 | ||
| Supply current configured, Hi-Speed host, USB2514B | IHCH1 | 70 | 80 | mA | Base current of one downstream port | 41 | |
| Supply current configured, Full-Speed host, USB2514B | IFCC1 | 50 | 60 | mA | Base current of one downstream port | 42 | |
| Supply current suspend, USB2514B | ICSBY | 550 | 1200 | µA | All supplies combined | 42 | |
| Supply current reset, USB2514B | ICRST | 750 | 1400 | µA | All supplies combined | 42 | |
| Clock Input Capacitance | CXTAL | 6 | pF | All pins except USB pins and the pins under test tied to AC ground | 42 | ||
| Input Capacitance | CIN | 6 | pF | Note 6-5 | 42 | ||
| Output Capacitance | COUT | 6 | pF | 42 | |||
| RESET_N asserted | t1 | 1 | µs | 36 | |||
| CFG_SEL[1:0] setup time | t2 | 16.7 | ns | 36 | |||
| CFG_SEL[1:0] hold time | t3 | 16.7 | 1400 | ns | 36 | ||
| Crystal frequency | -350 | 350 | ppm | 24 MHz parallel resonant fundamental mode crystal | 44 | ||
| Supply current, each additional downstream port (Hi-Speed host) | 25 | mA | 1 port base + 25 mA | 41 |
CAD (KiCad official)
- Symbol:
USB2514BT - Footprint:
Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm - 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
usb2514bt-etched.step/usb2514bt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb2514bt.step/usb2514bt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (57 pp, sha256
3fca1a17701a3fd5, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).