USB2513BI-AEZG from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USBDM_DN1/PRT_DIS_M1	bidirectional	Downstream port 1 hi-speed USB D- data line that also serves as a port-disable strap sampled at RESET_N negation, where pulling up both PRT_DIS_M1 and PRT_DIS_P1 disables the port.
2	USBDP_DN1/PRT_DIS_P1	bidirectional	Downstream port 1 hi-speed USB D+ data line that also serves as a port-disable strap, and a 10 k pull-up resistor to 3.3 V disables the port.
3	USBDM_DN2/PRT_DIS_M2	bidirectional	Downstream port 2 hi-speed USB D- data line that also serves as a port-disable strap sampled at RESET_N negation.
4	USBDP_DN2/PRT_DIS_P2	bidirectional	Downstream port 2 hi-speed USB D+ data line that also serves as a port-disable strap, and a 10 k pull-up resistor to 3.3 V disables the port.
5	VDDA33	power_in	3.3 V analog power supply.
6	USBDM_DN3/PRT_DIS_M3	bidirectional	Downstream port 3 hi-speed USB D- data line that also serves as a port-disable strap sampled at RESET_N negation.
7	USBDP_DN3/PRT_DIS_P3	bidirectional	Downstream port 3 hi-speed USB D+ data line that also serves as a port-disable strap, and a 10 k pull-up resistor to 3.3 V disables the port.
8	NC	unconnected	No connect: no signal or trace should be routed or attached to this pin.
9	NC	unconnected	No connect: no signal or trace should be routed or attached to this pin.
10	VDDA33	power_in	3.3 V analog power supply.
11	TEST	input	Test pin with internal pull-down that should be treated as a no connect or connected to ground, with no trace or signal routed or attached to it.
12	PRTPWR1/BC_EN1	bidirectional	Port 1 power enable output (O12) that is also the battery charging strap option (internal pull-down), sampled at RESET_N negation to enable the battery charging protocol.
13	OCS_N1	input	Over-current sense input for port 1 from an external current monitor, with internal pull-up.
14	CRFILT	passive	Core regulator filter capacitor pin that can have up to a 0.1 uF low-ESR capacitor to VSS, or be left unconnected.
15	VDD33	power_in	3.3 V digital power supply.
16	PRTPWR2/BC_EN2	bidirectional	Port 2 power enable output (O12) that is also the battery charging strap option (internal pull-down), sampled at RESET_N negation.
17	OCS_N2	input	Over-current sense input for port 2 from an external current monitor, with internal pull-up.
18	PRTPWR3/BC_EN3	bidirectional	Port 3 power enable output (O12) that is also the battery charging strap option (internal pull-down), sampled at RESET_N negation.
19	OCS_N3	input	Over-current sense input for port 3 from an external current monitor, with internal pull-up.
20	NC	unconnected	No connect: no signal or trace should be routed or attached to this pin.
21	NC	unconnected	No connect: no signal or trace should be routed or attached to this pin.
22	SDA/SMBDATA/NON_REM1	bidirectional	Serial data (I2C) or SMBus data signal (I/OSD12) that doubles as the Non-Removable Port 1 strap option, sampled with NON_REM0 at RESET_N negation.
23	VDD33	power_in	3.3 V digital power supply.
24	SCL/SMBCLK/CFG_SEL0	bidirectional	Serial clock (I2C) or SMBus clock (I/OSD12) whose logic state is latched on the rising edge of RESET_N as the configuration select CFG_SEL0.
25	HS_IND/CFG_SEL1	bidirectional	Hi-speed upstream port indicator (asserted when connected at HS, negated at FS) whose logic state is latched at RESET_N negation as configuration select CFG_SEL1.
26	RESET_N	input	Reset input that resets the chip when driven low, with a minimum active-low pulse of 1 us.
27	VBUS_DET	input	Detects the state of upstream VBUS power to decide when to assert the internal D+ pull-up, connected via a 2:1 divider (two 100 k resistors suggested) for detachable hubs.
28	SUSP_IND/LOCAL_PWR/NON_REM0	bidirectional	Active/suspend status LED output, local self-power detect input (low means no local power, high means available) and Non-Removable 0 strap sampled at RESET_N negation.
29	VDDA33	power_in	3.3 V analog power supply.
30	USBDM_UP	bidirectional	Upstream USB D- data signal that connects to the upstream USB bus (host, port, or upstream hub).
31	USBDP_UP	bidirectional	Upstream USB D+ data signal that connects to the upstream USB bus (host, port, or upstream hub).
32	XTALOUT	output	Crystal output, the other terminal of the 24 MHz crystal circuit with 1.2 V p-p output and weak (<1 mA) drive, left unconnected when an external clock drives XTALIN/CLKIN.
33	XTALIN/CLKIN	input	24 MHz crystal input that connects to one terminal of the crystal or to an external 24 MHz clock when no crystal is used.
34	PLLFILT	passive	PLL regulator filter capacitor pin that can have up to a 0.1 uF low-ESR capacitor to VSS, or be left unconnected.
35	RBIAS	passive	USB transceiver bias pin that requires a 12.0 k (+/-1%) resistor from this pin to ground to set the transceiver's internal bias.
36	VDDA33	power_in	3.3 V analog power supply.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-36-EP(6x6)
Category	Interface ICs
Pins	37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature	TSTOR	-55		150	°C		39
3.3 V supply voltage	VDD33, VDDA33			4.6	V	Applies to all packages	39
Voltage on any I/O pin		-0.5		5.5	V		39
Voltage on XTALIN		-0.5		4	V		39
Voltage on XTALOUT		-0.5		2.5	V		39
Industrial Operating Temperature	TAI	-40		85	°C	Ambient temperature in still air; only applies to USB251xBi products	39
3.3 V supply voltage	VDD33, VDDA33	3		3.6	V	Applies to all parts	39
3.3 V supply rise time	tRT33	0		400	us	See Figure 6-1 and Note 6-2	39
Voltage on any I/O pin (operating)		-0.3		5.5	V	If any 3.3 V supply voltage drops below 3.0 V, MAX becomes (3.3 V supply voltage) + 0.5	39
Voltage on XTALIN (operating)		-0.3			V	Max printed as VDD33 V	39
Low Input Level (I, IS buffer)	VILI			0.8	V	TTL Levels	40
High Input Level (I, IS buffer)	VIHI	2			V		40
Input Leakage (I, IS buffer)	IIL	-10		10	µA	VIN = 0 to VDD33	40
Hysteresis (IS only)	VHYSI	250		350	mV		40
Low Input Leakage (IPU buffer)	IILL	35		90	µA	VIN = 0	40
High Input Leakage (IPU buffer)	IIHL	-10		10	µA	VIN = VDD33	40
Low Input Leakage (IPD buffer)	IILL	10		-10	µA	VIN = 0	40
High Input Leakage (IPD buffer)	IIHL	-35		-90	µA	VIN = VDD33	40
Low Input Level (ICLK buffer)	VILCK			0.3	V		40
High Input Level (ICLK buffer)	VIHCK	0.9			V		40
Input Leakage (ICLK buffer)	IIL	-10		10	µA	VIN = 0 to VDD33	40
Low Output Level (O12, I/O12, I/OSD12)	VOL			0.4	V	IOL = 12 mA @ VDD33 = 3.3 V	41
High Output Level (O12, I/O12, I/OSD12)	VOH	2.4			V	IOH = -12 mA @ VDD33 = 3.3 V	41
Output Leakage (O12, I/O12, I/OSD12)	IOL	-10		10	µA	Output leakage; pins in high impedance (Note 6-3)	41
Hysteresis (SD pad only)	IHYSC	250		350	mV	VIN = VDD33 (Note 6-1)	41
Supply Current Unconfigured: Hi-Speed Host (USB2513Bi)	ICCINTHS		40	45	mA	Unconfigured; USB2513B/13Bi row	41
Supply Current Unconfigured: Full-Speed Host (USB2513Bi)	ICCINTFS		35	40	mA	Unconfigured; USB2513B/13Bi row	41
Supply Current Configured: Hi-Speed Host, base (USB2513Bi)	IHCH1	65		75	mA	Base current of one downstream port; each additional port adds 1 port base + 25 mA	41
Supply Current Configured: Full-Speed Host, base (USB2513Bi)	IFCC1	50		60	mA	Base current of one downstream port; each additional port adds 1 port base + 8 mA	42
Supply Current Suspend (USB2513Bi)	ICSBY	500		1300	µA	All supplies combined	42
Supply Current Reset (USB2513Bi)	ICRST	650		1400	µA	All supplies combined	42
Clock Input Capacitance	CXTAL		6		pF	All pins except USB pins and the pins under the test tied to AC ground	42
Input Capacitance	CIN		6		pF	Note 6-5: TA = 25°C; fc = 1 MHz; VDD33 = 3.3 V	42
Output Capacitance	COUT		6		pF	Note 6-5: TA = 25°C; fc = 1 MHz; VDD33 = 3.3 V	42
Supply current while RESET_N asserted				500	µA	Hub and associated circuitry consumption from upstream USB source while reset asserted	35
Crystal frequency tolerance		-350		350	ppm	Parallel resonant, fundamental mode, 24 MHz crystal	44
External clock duty cycle		-10	50	10	%	External clock, 50% duty cycle ±10%	45
External clock frequency tolerance		-350	24	350	ppm	External clock 24 MHz ±350 ppm (typ column holds the 24 MHz nominal)	45
External clock jitter				100	ps rms	External clock, jitter < 100 ps rms	45
RESET_N asserted	t1	1			s	Minimum RESET_N assertion after all power supplies are within operating range	36
CFG_SEL[1:0] setup time	t2	16.7			ns	RESET_N strapping option configuration	36
CFG_SEL[1:0] hold time	t3	16.7		1400	ns	RESET_N strapping option configuration	36
Hub outputs driven to inactive logic states	t4	1.5		2	s	RESET_N strapping option configuration	36
SMBus slave device timeout	TTIMEOUT	25		35	ms	Clock-low timeout: abort at 25 ms min (TTIMEOUT,MIN); slave must accept START by 35 ms max (TTIMEOUT,MAX)	34

CAD (KiCad official)

Symbol: USB2513BI-AEZG
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: usb2513bi-aezg-etched.step / usb2513bi-aezg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); usb2513bi-aezg.step / usb2513bi-aezg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (57 pp, sha256 82c76b8d64dfae7b, retrieved 2026-11-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

USB2513BI-AEZG

Verified USB2513BI-AEZG

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README