# USB2512B-AEZG-TR

**Microchip Tech** · USB ICs · QFN-36(6x6)

USB2512B-AEZG-TR from Microchip Tech, in a QFN-36(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USBDM_DN1/PRT_DIS_M1 | bidirectional | Downstream port 1 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation (pull up both PRT_DIS_M1 and PRT_DIS_P1 to disable the port). |
| 2 | USBDP_DN1/PRT_DIS_P1 | bidirectional | Downstream port 1 hi-speed USB D+ data, also the port-disable strap; to disable, use a 10 k pull-up resistor to 3.3 V. |
| 3 | USBDM_DN2/PRT_DIS_M2 | bidirectional | Downstream port 2 hi-speed USB D- data, also the port-disable strap sampled at RESET_N negation. |
| 4 | USBDP_DN2/PRT_DIS_P2 | bidirectional | Downstream port 2 hi-speed USB D+ data, also the port-disable strap; to disable, use a 10 k pull-up resistor to 3.3 V. |
| 5 | VDDA33 | power_in | 3.3 V analog power. |
| 6 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 7 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 8 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 9 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 10 | VDDA33 | power_in | 3.3 V analog power. |
| 11 | TEST | input | Test pin with internal pull-down; treat as no connect or connect to ground, with no trace or signal routed to it. |
| 12 | PRTPWR1/BC_EN1 | bidirectional | Enables power to downstream port 1 devices (O12 output) and, with internal pull-down, is the battery charging strap sampled at RESET_N negation (1 = supported). |
| 13 | OCS_N1 | input | Over-current sense input for port 1 from an external current monitor, with internal pull-up. |
| 14 | CRFILT | passive | Core regulator filter capacitor pin; up to a 0.1 uF low-ESR capacitor to VSS, or leave unconnected. |
| 15 | VDD33 | power_in | 3.3 V digital power. |
| 16 | PRTPWR2/BC_EN2 | bidirectional | Enables power to downstream port 2 devices (O12 output) and, with internal pull-down, is the battery charging strap sampled at RESET_N negation. |
| 17 | OCS_N2 | input | Over-current sense input for port 2 from an external current monitor, with internal pull-up. |
| 18 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 19 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 20 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 21 | NC | unconnected | No connect; no signal or trace should be routed or attached. |
| 22 | SDA/SMBDATA/NON_REM1 | bidirectional | Serial data (I2C) or SMBus data signal, also the non-removable port 1 strap sampled with NON_REM0 at RESET_N negation. |
| 23 | VDD33 | power_in | 3.3 V digital power. |
| 24 | SCL/SMBCLK/CFG_SEL0 | bidirectional | Serial clock (I2C) or SMBus clock, also configuration select latched at RESET_N negation to set the hub configuration method. |
| 25 | HS_IND/CFG_SEL1 | bidirectional | Hi-speed upstream port indicator (asserted = connected at HS), also configuration select 1 latched at RESET_N negation. |
| 26 | RESET_N | input | Active-low reset input; the minimum active low pulse is 1 us. |
| 27 | VBUS_DET | input | Detects upstream VBUS power to determine when to assert the internal D+ pull-up; connect via a 2:1 divider (two 100 k suggested) to VBUS, or to a host control output or the host 3.3 V domain when self-powered. |
| 28 | SUSP_IND/LOCAL_PWR/NON_REM0 | bidirectional | Active/suspend status LED indicator, local self-power detect (high = available), and non-removable port strap bit 0 sampled at RESET_N negation. |
| 29 | VDDA33 | power_in | 3.3 V analog power. |
| 30 | USBDM_UP | bidirectional | Upstream USB D- data; connect to the upstream USB bus data signals (host, port, or upstream hub). |
| 31 | USBDP_UP | bidirectional | Upstream USB D+ data; connect to the upstream USB bus data signals (host, port, or upstream hub). |
| 32 | XTALOUT | output | Crystal output with 1.2 V p-p and weak (<1 mA) drive; leave unconnected or use with caution when an external clock drives XTALIN/CLKIN. |
| 33 | XTALIN/CLKIN | input | 24 MHz crystal input, or external 24 MHz clock input when a crystal is not used. |
| 34 | PLLFILT | passive | PLL regulator filter capacitor pin; up to a 0.1 uF low-ESR capacitor to VSS, or leave unconnected. |
| 35 | RBIAS | input | USB transceiver bias; attach a 12.0 k (+/-1%) resistor from this pin to ground. |
| 36 | VDDA33 | power_in | 3.3 V analog power. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36(6x6) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 37 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 3.3 V supply voltage (absolute max) | VDD33, VDDA33 |  |  | 4.6 | V | Applies to all packages | 39 |
| Storage temperature | TSTOR | -55 |  | 150 | °C |  | 39 |
| Voltage on any I/O pin (abs max) |  | -0.5 |  | 5.5 | V |  | 39 |
| Voltage on XTALIN (abs max) |  | -0.5 |  | 4 | V |  | 39 |
| Voltage on XTALOUT (abs max) |  | -0.5 |  | 2.5 | V |  | 39 |
| Extended commercial operating temperature | TAE | 0 |  | 85 | °C | Ambient temperature in still air | 39 |
| 3.3 V supply voltage | VDD33, VDDA33 | 3 |  | 3.6 | V | Applies to all parts | 39 |
| 3.3 V supply rise time | tRT33 | 0 |  | 400 | µs | See Figure 6-1 and Note 6-2 | 39 |
| Voltage on any I/O pin |  | -0.3 |  | 5.5 | V | If any 3.3 V supply drops below 3.0 V, MAX becomes (3.3 V supply voltage) + 0.5 | 39 |
| Voltage on XTALIN |  | -0.3 |  | 3.6 | V | Max printed as VDD33 | 39 |
| I/IS input low level | VILI |  |  | 0.8 | V | TTL Levels | 40 |
| I/IS input high level | VIHI | 2 |  |  | V | TTL Levels | 40 |
| I/IS input leakage | IIL | -10 |  | 10 | µA | VIN = 0 to VDD33 | 40 |
| Hysteresis (IS only) | VHYSI | 250 |  | 350 | mV |  | 40 |
| IPU low input leakage | IILL | 35 |  | 90 | µA | VIN = 0 | 40 |
| IPU high input leakage | IIHL | -10 |  | 10 | µA | VIN = VDD33 | 40 |
| IPD low input leakage | IILL | 10 |  | -10 | µA | VIN = 0 | 40 |
| IPD high input leakage | IIHL | -35 |  | -90 | µA | VIN = VDD33 | 40 |
| ICLK input low level | VILCK |  |  | 0.3 | V |  | 40 |
| ICLK input high level | VIHCK | 0.9 |  |  | V |  | 40 |
| ICLK input leakage | IIL | -10 |  | 10 | µA | VIN = 0 to VDD33 | 40 |
| O12 low output level | VOL |  |  | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 41 |
| O12 high output level | VOH | 2.4 |  |  | V | IOH = -12 mA @ VDD33 = 3.3 V | 41 |
| Output leakage | IOL | -10 |  | 10 | µA |  | 41 |
| Hysteresis (SD pad only) | IHYSC | 250 |  | 350 | mV | VIN = VDD33 (Note 6-1) | 41 |
| Supply current configured, Hi-Speed host, one port base | IHCH1 |  | 60 | 65 | mA | USB2512B; base current of one downstream port | 41 |
| Supply current unconfigured, Hi-Speed host | ICCINTHS |  | 40 | 45 | mA | USB2512B/12Bi | 41 |
| Supply current unconfigured, Full-Speed host | ICCINTFS |  | 35 | 40 | mA | USB2512B/12Bi | 41 |
| Supply current configured, Full-Speed host, one port base | IFCC1 |  | 45 | 50 | mA | USB2512B; base current of one downstream port | 42 |
| Supply current suspend | ICSBY |  | 475 | 1000 | µA | USB2512B; all supplies combined | 42 |
| Supply current reset | ICRST |  | 550 | 1100 | µA | USB2512B; all supplies combined | 42 |
| Clock input capacitance | CXTAL |  |  | 6 | pF | All pins except USB pins and the pins under test tied to AC ground | 42 |
| Input capacitance | CIN |  |  | 6 | pF | (Note 6-5) | 42 |
| Output capacitance | COUT |  |  | 6 | pF |  | 42 |
| RESET_N asserted | t1 | 1 |  |  | µs |  | 36 |
| CFG_SEL[1:0] setup time | t2 | 16.7 |  |  | ns |  | 36 |
| CFG_SEL[1:0] hold time | t3 | 16.7 |  | 1400 | ns |  | 36 |
| Crystal frequency |  |  | 24 |  | MHz | Parallel resonant, fundamental mode, ±350 ppm | 44 |

## CAD (KiCad official)

- Symbol: `USB2512B-AEZG-TR`
- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`
- 3D model: QFN-36(6x6) (KiCad packages3D, STEP)
- 3D model files: `usb2512b-aezg-tr-etched.step` / `usb2512b-aezg-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `usb2512b-aezg-tr.step` / `usb2512b-aezg-tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/usb2512b-aezg-tr-datasheet.pdf) (57 pp, sha256 `3fca1a17701a3fd5`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/usb2512b-aezg-tr-datasheet.pdf)