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USB2412-DZK
Public Made by Adomby adom
Microchip Tech USB ICs, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownUSB2412-DZK
Microchip Tech · USB ICs · QFN-28-EP(5x5)
USB2412-DZK from Microchip Tech, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | USBDP_DN1 | bidirectional | Downstream port 1 hi-speed USB D+ data line, connected to the downstream USB peripheral device. |
| 2 | USBDM_DN2 | bidirectional | Downstream port 2 hi-speed USB D- data line, connected to the downstream USB peripheral device. |
| 3 | USBDP_DN2 | bidirectional | Downstream port 2 hi-speed USB D+ data line, connected to the downstream USB peripheral device. |
| 4 | VDD33 | power_in | 3.3 V power supply pin, with a 3.0 V to 3.6 V operating range. |
| 5 | NC | unconnected | No connect: no signal or trace should be routed or attached to this pin. |
| 6 | TEST | input | Test input with internal weak pull-down; treat as a no connect or connect to ground, and route no trace or signal to it. |
| 7 | PRTPWR1 | output | USB power enable for downstream port 1, supporting active high power controllers only (I/O12 buffer, 12 mA sink and source). |
| 8 | OCS_N1 | input | Over-current sense input for port 1 from an external current monitor, with an internal pull-up to the 3.3 V supply. |
| 9 | CRFILT | passive | Core regulator filter capacitor pin that can have up to a 0.1 uF low-ESR capacitor to VSS, or be left unconnected. |
| 10 | VDD33 | power_in | 3.3 V power supply pin, with a 3.0 V to 3.6 V operating range. |
| 11 | PRTPWR2 | output | USB power enable for downstream port 2, supporting active high power controllers only (I/O12 buffer, 12 mA sink and source). |
| 12 | OCS_N2 | input | Over-current sense input for port 2 from an external current monitor, with an internal pull-up to the 3.3 V supply. |
| 13 | NON_REM1 | bidirectional | Non-removable port strap, sampled with NON_REM0 at RESET_N negation: 00 all ports removable, 01 port 1 non-removable, 10 and 11 ports 1 and 2 non-removable. |
| 14 | VDD33 | power_in | 3.3 V power supply pin, with a 3.0 V to 3.6 V operating range. |
| 15 | TEST1 | input | Test pin that must be connected to VSS. |
| 16 | HS_IND | bidirectional | Hi-speed upstream port indicator (asserted when connected at HS, negated at FS) that can drive an LED, and requires a 50 kOhm or higher resistor to ground when no LED is used. |
| 17 | RESET_N | input | Active-low Schmitt-trigger reset input where the minimum active low pulse is 1 us. |
| 18 | VBUS_DET | input | Detects the upstream VBUS power state to decide when to assert the internal D+ pull-up, connected via a 2 to 1 voltage divider in a detachable hub; the hub removes the D+ pull-up power within 10 seconds of VBUS going inactive. |
| 19 | SUSP_IND/NON_REM0 | bidirectional | Suspend status LED indicator (active high if NON_REM0 = 0, active low if NON_REM0 = 1) that is also the NON_REM0 non-removable port strap sampled at RESET_N negation. |
| 20 | VDD33 | power_in | 3.3 V power supply pin, with a 3.0 V to 3.6 V operating range. |
| 21 | USBDM_UP | bidirectional | Upstream USB D- data line, connected to the upstream USB bus (host, port, or upstream hub). |
| 22 | USBDP_UP | bidirectional | Upstream USB D+ data line, connected to the upstream USB bus (host, port, or upstream hub). |
| 23 | XTALOUT | output | 24 MHz crystal output with 1.2 V p-p swing and weak (< 1 mA) drive, left unconnected when an external clock drives XTALIN/CLKIN. |
| 24 | XTALIN/CLKIN | input | 24 MHz crystal input or external 24 MHz clock input when a crystal is not used. |
| 25 | PLLFILT | passive | PLL regulator filter capacitor pin that can have up to a 0.1 uF low-ESR capacitor to VSS, or be left unconnected. |
| 26 | RBIAS | passive | USB transceiver bias pin, with a 12.0 kOhm (+/- 1%) resistor attached from ground to set the transceiver's internal bias. |
| 27 | VDD33 | power_in | 3.3 V power supply pin, with a 3.0 V to 3.6 V operating range. |
| 28 | USBDM_DN1 | bidirectional | Downstream port 1 hi-speed USB D- data line, connected to the downstream USB peripheral device. |
| 29 | ePAD | power_in | Ground pad that must be connected to VSS and tied to ground with multiple vias. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-28-EP(5x5) |
| Category | Interface ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TSTOR | -55 | 150 | °C | 16 | ||
| Voltage on any I/O pin | -0.5 | 5.5 | V | 16 | |||
| Voltage on XTALIN | -0.5 | 4 | V | 16 | |||
| Voltage on XTALOUT | -0.5 | 2.5 | V | 16 | |||
| 3.3 V supply voltage (VDD33, PLLFILT, CRFILT) | VDD33 | 4.6 | V | 16 | |||
| Operating Temperature | TA | 0 | 70 | °C | Ambient temperature in still air. | 16 | |
| 3.3 V supply voltage | VDD33 | 3 | 3.6 | V | 16 | ||
| 3.3 V supply rise time | tRT | 0 | 400 | μs | See Figure 4.1 | 16 | |
| Voltage on any I/O pin | -0.3 | 5.5 | V | If any 3.3 V supply voltage drops below 3.0 V, then the MAX becomes: (3.3 V supply voltage) + 0.5 | 16 | ||
| Voltage on XTALIN | -0.3 | V | 16 | ||||
| Low Input Level (I, IS type buffer) | VILI | 0.8 | V | TTL Levels | 17 | ||
| High Input Level (I, IS type buffer) | VIHI | 2 | V | TTL Levels | 17 | ||
| Input Leakage (I, IS type buffer) | IIL | -10 | 10 | μA | VIN = 0 to VDD33 | 17 | |
| Hysteresis (IS only) | VHYSI | 250 | 350 | mV | IS only | 17 | |
| Low Input Level (IPU buffer) | VILI | 0.8 | V | TTL Levels | 17 | ||
| High Input Level (IPU buffer) | VIHI | 2 | V | TTL Levels | 17 | ||
| Low Input Leakage (IPU buffer) | IILL | 35 | 90 | μA | TTL Levels, VIN = 0 | 17 | |
| High Input Leakage (IPU buffer) | IIHL | -10 | 10 | μA | TTL Levels, VIN = VDD33 | 17 | |
| Low Input Level (IPD buffer) | VILI | 0.8 | V | TTL Levels | 17 | ||
| High Input Level (IPD buffer) | VIHI | 2 | V | TTL Levels | 17 | ||
| Low Input Leakage (IPD buffer) | IILL | 10 | -10 | μA | TTL Levels, VIN = 0 | 17 | |
| High Input Leakage (IPD buffer) | IIHL | -35 | -90 | μA | TTL Levels, VIN = VDD33 | 17 | |
| Low Input Level (ICLK buffer) | VILCK | 0.5 | V | 17 | |||
| High Input Level (ICLK buffer) | VIHCK | 1.4 | V | 17 | |||
| Input Leakage (ICLK buffer) | IIL | -10 | 10 | μA | VIN = 0 to VDD33 | 17 | |
| Low Output Level (O12, I/O12, I/OSD12 buffer) | VOL | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 18 | ||
| High Output Level (O12, I/O12, I/OSD12 buffer) | VOH | 2.4 | V | IOH = -12 mA @ VDD33 = 3.3 V | 18 | ||
| Output Leakage (O12, I/O12, I/OSD12 buffer) | IOL | -10 | 10 | μA | VIN = 0 to VDD33 (Note 4.1) | 18 | |
| Hysteresis (SD pad only) | VHYSC | 250 | 350 | mV | SD pad only | 18 | |
| Supply Current Unconfigured Hi-Speed Host | ICCINTHS | 40 | 45 | mA | 18 | ||
| Supply Current Unconfigured Full-Speed Host | ICCINTFS | 35 | 40 | mA | 18 | ||
| Supply Current Configured Hi-Speed Host, 1 downstream port | IHCH1 | 60 | 65 | mA | 18 | ||
| Supply Current Configured Full-Speed Host, 1 downstream port | IFCC1 | 45 | 50 | mA | There is no additional current for additional ports. | 18 | |
| Supply Current Suspend | ICSBY | 475 | 1000 | μA | All supplies combined | 18 | |
| Supply Current Reset | ICRST | 550 | 1100 | μA | All supplies combined | 18 | |
| Clock Input Capacitance | CXTAL | 6 | pF | All pins except USB pins and the pins under the test tied to AC ground. | 19 | ||
| Input Capacitance | CIN | 6 | pF | TA = 25°C, fc = 1 MHz, VDD33 = 3.3 V | 19 | ||
| Output Capacitance | COUT | 6 | pF | The maximum capacitance values include the full length of the pin pad. | 19 | ||
| Thermal Resistance, junction-to-ambient | ΘJA | 40.3 | °C/W | 0 m/s air velocity | 19 | ||
| Thermal Resistance, junction-to-ambient | ΘJA | 35.2 | °C/W | 1 m/s air velocity | 19 | ||
| Junction-to-Top-of-Package | ΨJT | 0.5 | °C/W | 0 m/s air velocity | 19 | ||
| Junction-to-Top-of-Package | ΨJT | 0.6 | °C/W | 1 m/s air velocity | 19 | ||
| RESET_N asserted (minimum active low pulse) | t1 | 1 | μsec | RESET_N asserted | 15 | ||
| Strap setup time | t2 | 16.7 | nsec | 15 | |||
| Strap hold time | t3 | 16.7 | 1400 | nsec | 15 | ||
| Hub outputs driven to inactive logic states | t4 | 1.5 | 2 | μsec | 15 |
CAD (KiCad official)
- Symbol:
USB2412-DZK - Footprint:
Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm - 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
usb2412-dzk-etched.step/usb2412-dzk-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb2412-dzk.step/usb2412-dzk.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (27 pp, sha256
be57c5268c327c19, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).