component
USB2240-AEZG-06
Public Made by Adomby adom
Microchip Tech Interface - Specialized, QFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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USB2240-AEZG-06
Microchip Tech · Interface - Specialized · QFN-36-EP(6x6)
USB2240-AEZG-06 from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LED | bidirectional | Can be used as an LED output, using an I/O12 buffer with 12 mA sink and 12 mA source capability. |
| 2 | USB+ | bidirectional | USB bus data signal connected to the USB 2.0 analog I/O as defined in the USB 2.0 Specification. |
| 3 | USB- | bidirectional | USB bus data signal connected to the USB 2.0 analog I/O as defined in the USB 2.0 Specification. |
| 4 | xD_D3 / SD_D1 / MS_D5 | bidirectional | Multiplexed bidirectional data signal (xD_D3 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 5 | xD_D2 / SD_D0 / MS_D4 | bidirectional | Multiplexed bidirectional data signal (xD_D2 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 6 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 7 | xD_D1 / SD_D7 / MS_D6 | bidirectional | Multiplexed bidirectional data signal (xD_D1 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 8 | xD_D0 / SD_D6 / MS_D7 | bidirectional | Multiplexed bidirectional data signal (xD_D0 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 9 | xD_nWP / SD_CLK / MS_BS | output | xD active-low write protect output with a permanently enabled weak pull-down; the pin is shared with SD clock and MS bus state functions. |
| 10 | xD_ALE / SD_D5 / MS_D1 | output | xD active-high address latch enable output with a permanently enabled weak pull-down. |
| 11 | xD_CLE / SD_CMD / MS_D0 | output | xD active-high command latch enable output with a permanently enabled weak pull-down. |
| 12 | xD_nWE | output | xD active-low write strobe output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 13 | VDD18 | power_in | +1.8 V core power; requires a 1.0 µF ±20% (ESR < 0.1 Ω) capacitor to VSS. |
| 14 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 15 | xD_nCE | output | xD active-low chip enable output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 16 | xD_nRE | output | xD active-low read strobe output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 17 | xD_nB/R | input | xD busy or data-ready input from the xD BSY/RDY pin, with an internal weak pull-up when the internal FET is used. |
| 18 | RESET_N | input | Active-low chip reset Schmitt-trigger input; the active-low pulse must be at least 1 µs wide. |
| 19 | xD_nCD | bidirectional | xD-Picture card detect pin (I/O12) that may be left unconnected if the socket is not used. |
| 20 | xD_D7 / SD_D4 / MS_D2 | bidirectional | Multiplexed bidirectional data signal (xD_D7 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 21 | CRD_PWR | power_out | Card power drive of 3.3 V at either 100 mA or 200 mA from the internal power FET, with fold-back short-circuit protection. |
| 22 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 23 | xD_D6 / SD_D3 / MS_D3 | bidirectional | Multiplexed bidirectional data signal (xD_D6 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 24 | MS_INS | input | Memory Stick card insertion input with an internal pull-up, which may be left unconnected if the socket is not used. |
| 25 | xD_D5 / SD_D2 | bidirectional | Multiplexed bidirectional data signal (xD_D5 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 26 | SD_nCD | input | SD card detect input with an internal pull-up enabled at reset. |
| 27 | RXD / SDA | bidirectional | RXD is a UART receive input when custom firmware is used; SDA is the I/O data pin for an external serial EEPROM. |
| 28 | TEST | input | Test input that must be tied to ground for normal operation. |
| 29 | NC | unconnected | No connect; no trace or signal should be routed or attached to this pin. |
| 30 | xD_D4 / SD_WP / MS_SCLK | bidirectional | Multiplexed bidirectional data signal (xD_D4 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 31 | TXD / SCK / MS_SKT_SEL | bidirectional | TXD is a UART transmit output (custom firmware), SCK is the EEPROM clock output, and MS_SKT_SEL is sampled on the rising edge of RESET_N to select Memory Stick socket size (1 = 8-bit, 0 = 4-bit). |
| 32 | XTAL2 | output | Other terminal of the 24 MHz crystal; left open when an external clock drives XTAL1 (CLKIN). |
| 33 | XTAL1 (CLKIN) | input | One terminal of the 24 MHz crystal or an external 24 MHz clock input when no crystal is used. |
| 34 | VDD18PLL | power_in | +1.8 V filtered analog power for the internal PLL; requires a 1.0 µF ±20% (ESR < 0.1 Ω) capacitor to VSS. |
| 35 | RBIAS | passive | A 12.0 kΩ ±1.0% resistor from VSS to this pin sets the USB transceiver's internal bias currents. |
| 36 | VDDA33 | power_in | 3.3 V analog power supply for the USB analog circuitry. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36-EP(6x6) |
| Category | Interface |
| Pins | 37 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TA | -55 | 150 | °C | 31 | ||
| 3.3 V supply voltage (absolute maximum) | VDD33 | -0.5 | 4 | V | 31 | ||
| Voltage on USB+ and USB- pins (absolute maximum) | -0.5 | 6 | V | Printed as (3.3 V supply voltage + 2) ≤ 6 V | 31 | ||
| Voltage on CRD_PWR (absolute maximum) | -0.5 | V | Max printed as VDD33 + 0.3 V; internal power FET operation enabled | 31 | |||
| Voltage on any signal pin (absolute maximum) | -0.5 | V | Max printed as VDD33 + 0.3 V | 31 | |||
| Voltage on XTAL1 (absolute maximum) | -0.5 | 3.6 | V | 31 | |||
| Voltage on XTAL2 (absolute maximum) | -0.5 | V | Max printed as VDD18 + 0.3 V | 31 | |||
| Operating temperature, commercial part | TA | 0 | 70 | °C | Commercial part; ambient temperature in still air | 32 | |
| 3.3 V supply voltage | VDD33 | 3 | 3.6 | V | Note 9-3 | 32 | |
| 3.3 V supply rise time | tRT | 0 | 400 | μs | 32 | ||
| Voltage on USB+ and USB- pins | -0.3 | 5.5 | V | If 3.3 V supply drops below 3.0 V, max becomes (3.3 V supply) + 0.5 ≤ 5.5 V | 32 | ||
| Voltage on any signal pin | -0.3 | V | Max printed as VDD33 | 32 | |||
| Voltage on XTAL1 | -0.3 | V | Max printed as VDD33 | 32 | |||
| Voltage on XTAL2 | -0.3 | V | Max printed as VDD18 | 32 | |||
| High input level, I/IPU/IPD buffer | VIHI | 2 | V | TTL levels | 32 | ||
| Low input level, I/IPU/IPD buffer | VILI | 0.8 | V | TTL levels | 32 | ||
| Low input level, ICLK buffer | VILCK | 0.5 | V | 32 | |||
| High input level, ICLK buffer | VIHCK | 1.4 | V | 32 | |||
| Input leakage, ICLK buffer | IIL | -10 | 10 | μA | VIN = 0 to VDD33 | 32 | |
| High input level, IS buffer | VIHI | 2 | V | TTL levels | 32 | ||
| Low input level, IS buffer | VILI | 0.8 | V | TTL levels | 32 | ||
| Input leakage, all I and IS buffers (low) | IIL | -10 | 10 | μA | VIN = 0 | 33 | |
| Input leakage, all I and IS buffers (high) | IIH | -10 | 10 | μA | VIN = VDD33 | 33 | |
| Low output level, O12 buffer | VOL | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 33 | ||
| Output leakage, O12 buffer | IOL | -10 | 10 | μA | VIN = 0 to VDD33 (Note 9-4) | 33 | |
| Low output level, I/O12 buffer | VOL | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 33 | ||
| Output leakage, I/O12 buffer | IOL | -10 | 10 | μA | VIN = 0 to VDD33 (Note 9-4) | 33 | |
| Supply current unconfigured | ICCINIT | 80 | 90 | mA | 33 | ||
| Supply current active, full speed | ICC | 110 | 135 | mA | Full speed | 33 | |
| Supply current active, high speed | ICC | 140 | 165 | mA | High speed | 33 | |
| Supply current suspend | ICSBY | 350 | 700 | µA | 33 | ||
| Crystal frequency tolerance | -350 | 350 | ppm | Parallel resonant, fundamental mode, 24 MHz crystal | 35 | ||
| VDD18PLL filter capacitor tolerance | -20 | 20 | % | Capacitor to VSS | 16 | ||
| VDD18PLL filter capacitor ESR | ESR | 0.1 | Ω | ESR < 0.1 Ω | 16 | ||
| VDD18 core capacitor tolerance | -20 | 20 | % | Capacitor to VSS | 16 | ||
| VDD18 core capacitor ESR | ESR | 0.1 | Ω | ESR < 0.1 Ω | 16 | ||
| Pull-down current, I buffer | PD | 72 | μA | 32 | |||
| Pull-up current, I buffer | PU | 58 | μA | 32 | |||
| Hysteresis, IS buffer | VHYSI | 420 | mV | 32 | |||
| Pull-down current, I/O12 buffer | PD | 72 | μA | 33 | |||
| Pull-up current, I/O12 buffer | PU | 58 | μA | 33 | |||
| Integrated power FET high output current mode | IOUT | 200 | mA | VdropFET = 0.46 V | 33 | ||
| Integrated power FET low output current mode | IOUT | 100 | mA | VdropFET = 0.23 V | 33 | ||
| Power FET on resistance | RDSON | 2.1 | Ω | IFET = 70 mA | 33 | ||
| Power FET output voltage rise time | tDSON | 800 | μs | CLOAD = 10 μF | 33 | ||
| Clock input capacitance | CXTAL | 2 | pF | All pins except USB pins and pins under test tied to AC ground | 34 | ||
| Input capacitance | CIN | 10 | pF | 34 | |||
| Output capacitance | COUT | 20 | pF | 34 | |||
| Thermal resistance junction-to-ambient, 0 m/s | ΘJA | 33.2 | °C/W | Velocity 0 m/s | 34 | ||
| Thermal resistance junction-to-ambient, 1 m/s | ΘJA | 29 | °C/W | Velocity 1 m/s | 34 | ||
| Thermal resistance junction-to-ambient, 2 m/s | ΘJA | 26 | °C/W | Velocity 2 m/s | 34 | ||
| Junction-to-top-of-package, 0 m/s | ΨJT | 2.6 | °C/W | Velocity 0 m/s | 34 | ||
| Junction-to-top-of-package, 1 m/s | ΨJT | 2.6 | °C/W | Velocity 1 m/s | 34 | ||
| Junction-to-top-of-package, 2 m/s | ΨJT | 2.6 | °C/W | Velocity 2 m/s | 34 | ||
| Crystal load capacitor C1 (typical) | C1 | 18 | pF | Typical value; calculated per Figure 10-2 | 35 | ||
| Crystal load capacitor C2 (typical) | C2 | 18 | pF | Typical value; calculated per Figure 10-2 | 35 | ||
| VDD18PLL filter capacitor nominal | 1 | μF | Capacitor to VSS | 16 | |||
| VDD18 core capacitor nominal | 1 | μF | Capacitor to VSS | 16 |
CAD (KiCad official)
- Symbol:
USB2240-AEZG-06 - Footprint:
Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm - 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
usb2240-aezg-06-etched.step/usb2240-aezg-06-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);usb2240-aezg-06.step/usb2240-aezg-06.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (43 pp, sha256
3e98a6a324cc56bd, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# USB2240-AEZG-06
**Microchip Tech** · Interface - Specialized · QFN-36-EP(6x6)
USB2240-AEZG-06 from Microchip Tech, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LED | bidirectional | Can be used as an LED output, using an I/O12 buffer with 12 mA sink and 12 mA source capability. |
| 2 | USB+ | bidirectional | USB bus data signal connected to the USB 2.0 analog I/O as defined in the USB 2.0 Specification. |
| 3 | USB- | bidirectional | USB bus data signal connected to the USB 2.0 analog I/O as defined in the USB 2.0 Specification. |
| 4 | xD_D3 / SD_D1 / MS_D5 | bidirectional | Multiplexed bidirectional data signal (xD_D3 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 5 | xD_D2 / SD_D0 / MS_D4 | bidirectional | Multiplexed bidirectional data signal (xD_D2 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 6 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 7 | xD_D1 / SD_D7 / MS_D6 | bidirectional | Multiplexed bidirectional data signal (xD_D1 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 8 | xD_D0 / SD_D6 / MS_D7 | bidirectional | Multiplexed bidirectional data signal (xD_D0 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 9 | xD_nWP / SD_CLK / MS_BS | output | xD active-low write protect output with a permanently enabled weak pull-down; the pin is shared with SD clock and MS bus state functions. |
| 10 | xD_ALE / SD_D5 / MS_D1 | output | xD active-high address latch enable output with a permanently enabled weak pull-down. |
| 11 | xD_CLE / SD_CMD / MS_D0 | output | xD active-high command latch enable output with a permanently enabled weak pull-down. |
| 12 | xD_nWE | output | xD active-low write strobe output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 13 | VDD18 | power_in | +1.8 V core power; requires a 1.0 µF ±20% (ESR < 0.1 Ω) capacitor to VSS. |
| 14 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 15 | xD_nCE | output | xD active-low chip enable output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 16 | xD_nRE | output | xD active-low read strobe output with a weak pull-up tied to the internal power FET output when the internal FET is used. |
| 17 | xD_nB/R | input | xD busy or data-ready input from the xD BSY/RDY pin, with an internal weak pull-up when the internal FET is used. |
| 18 | RESET_N | input | Active-low chip reset Schmitt-trigger input; the active-low pulse must be at least 1 µs wide. |
| 19 | xD_nCD | bidirectional | xD-Picture card detect pin (I/O12) that may be left unconnected if the socket is not used. |
| 20 | xD_D7 / SD_D4 / MS_D2 | bidirectional | Multiplexed bidirectional data signal (xD_D7 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 21 | CRD_PWR | power_out | Card power drive of 3.3 V at either 100 mA or 200 mA from the internal power FET, with fold-back short-circuit protection. |
| 22 | VDD33 | power_in | 3.3 V power and regulator input; absolute maximum VDD33 rating is 4.0 V. |
| 23 | xD_D6 / SD_D3 / MS_D3 | bidirectional | Multiplexed bidirectional data signal (xD_D6 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 24 | MS_INS | input | Memory Stick card insertion input with an internal pull-up, which may be left unconnected if the socket is not used. |
| 25 | xD_D5 / SD_D2 | bidirectional | Multiplexed bidirectional data signal (xD_D5 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 26 | SD_nCD | input | SD card detect input with an internal pull-up enabled at reset. |
| 27 | RXD / SDA | bidirectional | RXD is a UART receive input when custom firmware is used; SDA is the I/O data pin for an external serial EEPROM. |
| 28 | TEST | input | Test input that must be tied to ground for normal operation. |
| 29 | NC | unconnected | No connect; no trace or signal should be routed or attached to this pin. |
| 30 | xD_D4 / SD_WP / MS_SCLK | bidirectional | Multiplexed bidirectional data signal (xD_D4 on USB2240) with 12 mA sink/source and a weak internal pull-down resistor. |
| 31 | TXD / SCK / MS_SKT_SEL | bidirectional | TXD is a UART transmit output (custom firmware), SCK is the EEPROM clock output, and MS_SKT_SEL is sampled on the rising edge of RESET_N to select Memory Stick socket size (1 = 8-bit, 0 = 4-bit). |
| 32 | XTAL2 | output | Other terminal of the 24 MHz crystal; left open when an external clock drives XTAL1 (CLKIN). |
| 33 | XTAL1 (CLKIN) | input | One terminal of the 24 MHz crystal or an external 24 MHz clock input when no crystal is used. |
| 34 | VDD18PLL | power_in | +1.8 V filtered analog power for the internal PLL; requires a 1.0 µF ±20% (ESR < 0.1 Ω) capacitor to VSS. |
| 35 | RBIAS | passive | A 12.0 kΩ ±1.0% resistor from VSS to this pin sets the USB transceiver's internal bias currents. |
| 36 | VDDA33 | power_in | 3.3 V analog power supply for the USB analog circuitry. |
| 37 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-36-EP(6x6) |
| Category | Interface |
| Pins | 37 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TA | -55 | | 150 | °C | | 31 |
| 3.3 V supply voltage (absolute maximum) | VDD33 | -0.5 | | 4 | V | | 31 |
| Voltage on USB+ and USB- pins (absolute maximum) | | -0.5 | | 6 | V | Printed as (3.3 V supply voltage + 2) ≤ 6 V | 31 |
| Voltage on CRD_PWR (absolute maximum) | | -0.5 | | | V | Max printed as VDD33 + 0.3 V; internal power FET operation enabled | 31 |
| Voltage on any signal pin (absolute maximum) | | -0.5 | | | V | Max printed as VDD33 + 0.3 V | 31 |
| Voltage on XTAL1 (absolute maximum) | | -0.5 | | 3.6 | V | | 31 |
| Voltage on XTAL2 (absolute maximum) | | -0.5 | | | V | Max printed as VDD18 + 0.3 V | 31 |
| Operating temperature, commercial part | TA | 0 | | 70 | °C | Commercial part; ambient temperature in still air | 32 |
| 3.3 V supply voltage | VDD33 | 3 | | 3.6 | V | Note 9-3 | 32 |
| 3.3 V supply rise time | tRT | 0 | | 400 | μs | | 32 |
| Voltage on USB+ and USB- pins | | -0.3 | | 5.5 | V | If 3.3 V supply drops below 3.0 V, max becomes (3.3 V supply) + 0.5 ≤ 5.5 V | 32 |
| Voltage on any signal pin | | -0.3 | | | V | Max printed as VDD33 | 32 |
| Voltage on XTAL1 | | -0.3 | | | V | Max printed as VDD33 | 32 |
| Voltage on XTAL2 | | -0.3 | | | V | Max printed as VDD18 | 32 |
| High input level, I/IPU/IPD buffer | VIHI | 2 | | | V | TTL levels | 32 |
| Low input level, I/IPU/IPD buffer | VILI | | | 0.8 | V | TTL levels | 32 |
| Low input level, ICLK buffer | VILCK | | | 0.5 | V | | 32 |
| High input level, ICLK buffer | VIHCK | 1.4 | | | V | | 32 |
| Input leakage, ICLK buffer | IIL | -10 | | 10 | μA | VIN = 0 to VDD33 | 32 |
| High input level, IS buffer | VIHI | 2 | | | V | TTL levels | 32 |
| Low input level, IS buffer | VILI | | | 0.8 | V | TTL levels | 32 |
| Input leakage, all I and IS buffers (low) | IIL | -10 | | 10 | μA | VIN = 0 | 33 |
| Input leakage, all I and IS buffers (high) | IIH | -10 | | 10 | μA | VIN = VDD33 | 33 |
| Low output level, O12 buffer | VOL | | | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 33 |
| Output leakage, O12 buffer | IOL | -10 | | 10 | μA | VIN = 0 to VDD33 (Note 9-4) | 33 |
| Low output level, I/O12 buffer | VOL | | | 0.4 | V | IOL = 12 mA @ VDD33 = 3.3 V | 33 |
| Output leakage, I/O12 buffer | IOL | -10 | | 10 | μA | VIN = 0 to VDD33 (Note 9-4) | 33 |
| Supply current unconfigured | ICCINIT | | 80 | 90 | mA | | 33 |
| Supply current active, full speed | ICC | | 110 | 135 | mA | Full speed | 33 |
| Supply current active, high speed | ICC | | 140 | 165 | mA | High speed | 33 |
| Supply current suspend | ICSBY | | 350 | 700 | µA | | 33 |
| Crystal frequency tolerance | | -350 | | 350 | ppm | Parallel resonant, fundamental mode, 24 MHz crystal | 35 |
| VDD18PLL filter capacitor tolerance | | -20 | | 20 | % | Capacitor to VSS | 16 |
| VDD18PLL filter capacitor ESR | ESR | | | 0.1 | Ω | ESR < 0.1 Ω | 16 |
| VDD18 core capacitor tolerance | | -20 | | 20 | % | Capacitor to VSS | 16 |
| VDD18 core capacitor ESR | ESR | | | 0.1 | Ω | ESR < 0.1 Ω | 16 |
| Pull-down current, I buffer | PD | | 72 | | μA | | 32 |
| Pull-up current, I buffer | PU | | 58 | | μA | | 32 |
| Hysteresis, IS buffer | VHYSI | | 420 | | mV | | 32 |
| Pull-down current, I/O12 buffer | PD | | 72 | | μA | | 33 |
| Pull-up current, I/O12 buffer | PU | | 58 | | μA | | 33 |
| Integrated power FET high output current mode | IOUT | | 200 | | mA | VdropFET = 0.46 V | 33 |
| Integrated power FET low output current mode | IOUT | | 100 | | mA | VdropFET = 0.23 V | 33 |
| Power FET on resistance | RDSON | | 2.1 | | Ω | IFET = 70 mA | 33 |
| Power FET output voltage rise time | tDSON | | 800 | | μs | CLOAD = 10 μF | 33 |
| Clock input capacitance | CXTAL | | 2 | | pF | All pins except USB pins and pins under test tied to AC ground | 34 |
| Input capacitance | CIN | | 10 | | pF | | 34 |
| Output capacitance | COUT | | 20 | | pF | | 34 |
| Thermal resistance junction-to-ambient, 0 m/s | ΘJA | | 33.2 | | °C/W | Velocity 0 m/s | 34 |
| Thermal resistance junction-to-ambient, 1 m/s | ΘJA | | 29 | | °C/W | Velocity 1 m/s | 34 |
| Thermal resistance junction-to-ambient, 2 m/s | ΘJA | | 26 | | °C/W | Velocity 2 m/s | 34 |
| Junction-to-top-of-package, 0 m/s | ΨJT | | 2.6 | | °C/W | Velocity 0 m/s | 34 |
| Junction-to-top-of-package, 1 m/s | ΨJT | | 2.6 | | °C/W | Velocity 1 m/s | 34 |
| Junction-to-top-of-package, 2 m/s | ΨJT | | 2.6 | | °C/W | Velocity 2 m/s | 34 |
| Crystal load capacitor C1 (typical) | C1 | | 18 | | pF | Typical value; calculated per Figure 10-2 | 35 |
| Crystal load capacitor C2 (typical) | C2 | | 18 | | pF | Typical value; calculated per Figure 10-2 | 35 |
| VDD18PLL filter capacitor nominal | | | 1 | | μF | Capacitor to VSS | 16 |
| VDD18 core capacitor nominal | | | 1 | | μF | Capacitor to VSS | 16 |
## CAD (KiCad official)
- Symbol: `USB2240-AEZG-06`
- Footprint: `Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm`
- 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `usb2240-aezg-06-etched.step` / `usb2240-aezg-06-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `usb2240-aezg-06.step` / `usb2240-aezg-06.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589804988085276672) (43 pp, sha256 `3e98a6a324cc56bd`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/usb2240-aezg-06-datasheet.pdf)