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UPD720210K8-BAF-A

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RENESAS USB ICs, QFN-76-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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UPD720210K8-BAF-A

RENESAS · USB ICs · QFN-76-EP(9x9)

UPD720210K8-BAF-A from RENESAS, in a QFN-76-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SUSPEND/NRDCLKO output Pin 1 outputs SUSPEND or the non-removable device clock (CLKOUT), selected by the pin strap settings of SPICSB and OCI1B, and is Hi-Z until configured.
2 RESETB input Active-low chip reset input, with the power-on reset timing given in the electrical specifications.
3 U3TXDP1 output USB 3.0 downstream port 1 SuperSpeed transmit D+ signal.
4 U3TXDN1 output USB 3.0 downstream port 1 SuperSpeed transmit D- signal.
5 VDD10 power_in 1.05 V power supply for the core logic.
6 U3RXDP1 input USB 3.0 downstream port 1 SuperSpeed receive D+ signal.
7 U3RXDN1 input USB 3.0 downstream port 1 SuperSpeed receive D- signal.
8 VDD33 power_in 3.3 V power supply for the IO buffers.
9 U2DP1 bidirectional USB 2.0 downstream port 1 D+ signal for High-/Full-/Low-speed.
10 U2DM1 bidirectional USB 2.0 downstream port 1 D- signal for High-/Full-/Low-speed.
11 VDD10 power_in 1.05 V power supply for the core logic.
12 U3TXDP2 output USB 3.0 downstream port 2 SuperSpeed transmit D+ signal.
13 U3TXDN2 output USB 3.0 downstream port 2 SuperSpeed transmit D- signal.
14 VDD10 power_in 1.05 V power supply for the core logic.
15 U3RXDP2 input USB 3.0 downstream port 2 SuperSpeed receive D+ signal.
16 U3RXDN2 input USB 3.0 downstream port 2 SuperSpeed receive D- signal.
17 VDD33 power_in 3.3 V power supply for the IO buffers.
18 U2DP2 bidirectional USB 2.0 downstream port 2 D+ signal for High-/Full-/Low-speed.
19 U2DM2 bidirectional USB 2.0 downstream port 2 D- signal for High-/Full-/Low-speed.
20 U3TXDP3 output USB 3.0 downstream port 3 SuperSpeed transmit D+ signal.
21 U3TXDN3 output USB 3.0 downstream port 3 SuperSpeed transmit D- signal.
22 VDD10 power_in 1.05 V power supply for the core logic.
23 U3RXDP3 input USB 3.0 downstream port 3 SuperSpeed receive D+ signal.
24 U3RXDN3 input USB 3.0 downstream port 3 SuperSpeed receive D- signal.
25 VDD33 power_in 3.3 V power supply for the IO buffers.
26 U2DP3 bidirectional USB 2.0 downstream port 3 D+ signal for High-/Full-/Low-speed.
27 U2DM3 bidirectional USB 2.0 downstream port 3 D- signal for High-/Full-/Low-speed.
28 VDD10 power_in 1.05 V power supply for the core logic.
29 U3TXDP4 output USB 3.0 downstream port 4 SuperSpeed transmit D+ signal.
30 U3TXDN4 output USB 3.0 downstream port 4 SuperSpeed transmit D- signal.
31 VDD10 power_in 1.05 V power supply for the core logic.
32 U3RXDP4 input USB 3.0 downstream port 4 SuperSpeed receive D+ signal.
33 U3RXDN4 input USB 3.0 downstream port 4 SuperSpeed receive D- signal.
34 VDD33 power_in 3.3 V power supply for the IO buffers.
35 U2DP4 bidirectional USB 2.0 downstream port 4 D+ signal for High-/Full-/Low-speed.
36 U2DM4 bidirectional USB 2.0 downstream port 4 D- signal for High-/Full-/Low-speed.
37 LED1B/SUSPEND output Port 1 LED control output (Green only) when the external ROM is not used, or SUSPEND output when the external ROM is used and SUSPEND is enabled.
38 SPICSB bidirectional External serial ROM chip select (active low), also used as a pin strap input for ROM, LED and ROM address length options.
39 SPISI/LED2B bidirectional External serial ROM data output to the ROM SI input, or LED2 output depending on pin strap setting.
40 SPISO/LED3B bidirectional External serial ROM data input from the ROM SO output, or LED3 output depending on pin strap setting.
41 SPISCK/LED4B bidirectional External serial ROM clock output, or LED4 output depending on pin strap setting.
42 VDD33 power_in 3.3 V power supply for the IO buffers.
43 VBUSM input Upstream port VBUS monitor input, which takes VBUS divided down to 3.3 V.
44 BUSSEL input Power mode select input: 0 selects bus-power and 1 selects self-power.
45 OCI1B input Port 1 over-current input (active low), which also selects non-removable setting when low as a pin strap.
46 PPON1B/NRDRSTB bidirectional Port 1 power control output (active low) when high, or non-removable device reset NRDRSTB when strapped low.
47 VDD10 power_in 1.05 V power supply for the core logic.
48 V33OUT power_out LDO 3.3 V output; 15 kΩ and 4.7 μF are required between this pin and GND when the integrated LDO is not used.
49 V50IN power_in LDO regulator 5 V input, which must be connected to GND when the integrated LDO is not used.
50 AVDD33R power_in Switching regulator 3.3 V input.
51 PGDRV output Switching regulator P-channel FET control output; see section 3.10 for FET selection.
52 NGDRV output Switching regulator N-channel FET control output; see section 3.10 for FET selection.
53 ILIM input Switching regulator current sense input.
54 V10FB input Switching regulator output voltage monitor input for the 1.05 V output.
55 OCI2B input Port 2 over-current input (active low), which also selects non-removable setting when low as a pin strap.
56 PPON2B bidirectional Port power control output for port 2 (active low) that also sets gang or individual power control mode as a pin strap.
57 OCI3B input Port 3 over-current input (active low), which also selects non-removable setting when low as a pin strap.
58 PPON3B bidirectional Port 3 power control output (active low) that also sets the number of ports as a pin strap.
59 OCI4B input Port 4 over-current input (active low), which also selects non-removable setting when low as a pin strap.
60 PPON4B bidirectional Port 4 power control output (active low) that also sets the number of ports as a pin strap.
61 VDD33 power_in 3.3 V power supply for the IO buffers.
62 U2DPU bidirectional USB 2.0 upstream D+ signal for High-/Full-/Low-speed.
63 U2DMU bidirectional USB 2.0 upstream D- signal for High-/Full-/Low-speed.
64 VDD10 power_in 1.05 V power supply for the core logic.
65 U3TXDNU output USB 3.0 upstream SuperSpeed transmit D- signal.
66 U3TXDPU output USB 3.0 upstream SuperSpeed transmit D+ signal.
67 VDD10 power_in 1.05 V power supply for the core logic.
68 U3RXDNU input USB 3.0 upstream SuperSpeed receive D- signal.
69 U3RXDPU input USB 3.0 upstream SuperSpeed receive D+ signal.
70 VDD10 power_in 1.05 V power supply for the core logic.
71 AVDD33 power_in 3.3 V power supply for the analog circuits.
72 RREF passive Reference voltage input for USB 2.0, which must be connected to a 1.6 kΩ resistor with 1% tolerance.
73 IC(L) input Test pin that must be connected to GND.
74 XT1 input External oscillator input connected to a 24 MHz crystal; it can also be driven by a 3.3 V oscillator.
75 XT2 output External oscillator output connected to a 24 MHz crystal; left open when XT1 is driven single-ended.
76 VDD33 power_in 3.3 V power supply for the IO buffers.
77 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-76-EP(9x9)
Category Interface ICs
Pins 77

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VDD33, AVDD33 -0.5 4.6 V 15
Power supply voltage VDD10 -0.5 1.4 V 15
Power supply voltage V50IN 5.5 V 15
Input voltage, 3.3 V buffer VI -0.5 4.6 V VI < VDD33 + 0.5 V 15
Output voltage, 3.3 V buffer VO -0.5 4.6 V VO < VDD33 + 0.5 V 15
USB3.0 differential signals VI/VO -0.5 1.4 V VI/VO < VDD10 + 0.5 V 15
Input voltage, 5 V buffer VI -0.5 6.6 V VI < VDD33 + 2.5 V 15
Output current, 4 mA type IO 8 mA 4 mA Type buffer 15
Output current, 12 mA type IO 24 mA 12 mA Type buffer 15
Storage temperature Tstg -65 125 °C 15
Operating voltage with external power source VDD33, AVDD33 3 3.3 3.6 V With external power source 15
Operating voltage VDD10 0.9975 1.05 1.1025 V 15
Operating voltage with on-chip regulators V50IN 4.75 5 5.25 V With on-chip Regulators 15
High-level input voltage VIH 2 V 15
Low-level input voltage VIL -0.3 0.8 V 15
Input rise time, normal buffer Tri 0 200 ns Normal Buffer 15
Input rise time, Schmitt buffer Tri 0 10 ms Schmitt Buffer 15
Input fall time, normal buffer Tfi 0 200 ns Normal Buffer 15
Input fall time, Schmitt buffer Tfi 0 10 ms Schmitt Buffer 15
Operating ambient temperature TA 0 70 °C 15
Off-state output current IOZ -10 10 μA VI = VDD33 or GND 16
Input leakage current II -10 10 μA VI = VDD33 or GND 16
Low-level output voltage VOL 0.1 V IOL = 0 mA 16
Output pin impedance ZHSDRV 40.5 49.5 Ω 16
High-level input voltage (drive) VIH 2 V Input levels for Low-/Full-speed 16
High-level input voltage (floating) VIHZ 2.7 3.6 V Input levels for Low-/Full-speed 16
Low-level input voltage VIL 0.8 V Input levels for Low-/Full-speed 16
Differential input sensitivity VDI 0.2 V /(D+) - (D-)/ 16
Differential common mode range VCM 0.8 2.5 V Includes VDI range 16
High-level output voltage VOH 2.8 3.6 V RL of 14.25 kΩ to GND 16
Low-level output voltage VOL 0 0.3 V RL of 1.425 kΩ to 3.6 V 16
SE1 output voltage VOSE1 0.8 V 16
Output signal crossover point voltage VCRS 1.3 2 V 16
High-speed squelch detection threshold (differential signal) VHSSQ 100 150 mV 16
High-speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV 16
High-speed data signaling common mode voltage range VHSCM -50 500 mV 16
High-speed idle state VHSOI -10 10 mV 16
High-speed data signaling high VHSOH 360 440 mV 16
High-speed data signaling low VHSOL -10 10 mV 16
Chirp J level (differential signal) VCHIRPJ 700 1100 mV 16
Chirp K level (differential signal) VCHIRPK -900 -500 mV 16
Cut-off current of on-chip regulator (1.05 V) Icutoff1 1.4 1.8 A 18
Cut-off current of on-chip regulator (3.3 V) Icutoff3 0.8 1.2 A 18
SPI interface pin capacitance CSPI 5 pF 19
Clock frequency tolerance FCLK -100 100 ppm Crystal 20
Clock frequency FCLK 24 MHz Crystal 20
Clock duty cycle TDUTY 40 50 60 % 20
Power on reset time TPONRST 10 ms See Figure 3-7 21
Clock out timing after reset out ends TRSTtoCLK 300 μs See Figure 3-8 21
Reset timing for non-removable device after clock out starts TCLKtoRSTE 30 ms See Figure 3-8 21
Unit interval UI 199.94 200.06 ps 26
Receiver DC common mode impedance RRX-DC 18 30 Ω 26
DC differential impedance RRX-DIFF-DC 72 120 Ω 26
DC input CM input impedance for V>0 during reset of power down ZRX-HIGH-IMP-DC-POS 25 kΩ 26
LFPS detect threshold VRX-LFPS-DET-DIFF-p-p 100 300 mV 26
Max Rx inherent timing error TRX-Tj 0.45 UI 26
Max Rx inherent deterministic timing error TRX-DJ-DD 0.285 UI 26
Rx input capacitance for return loss CRX-PARASITIC 1.1 pF 26
Rx AC common mode voltage VRX-CM-AC-P 150 mVPeak 26

CAD (KiCad official)

  • Symbol: UPD720210K8-BAF-A
  • Footprint: Package_DFN_QFN:QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm
  • 3D model: QFN-76-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: upd720210k8-baf-a-etched.step / upd720210k8-baf-a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); upd720210k8-baf-a.step / upd720210k8-baf-a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (44 pp, sha256 4142aaed32d66c0e, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF