component

UPD720202K8-711-BAA-A

Public Made by Adom

by adom

RENESAS USB ICs, QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232upd720202k8-711-baa-afactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

UPD720202K8-711-BAA-A

RENESAS · USB ICs · QFN-48(7x7)

UPD720202K8-711-BAA-A from RENESAS, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PECLKP input PCI Express 100 MHz reference clock, positive side of the differential pair.
2 PECLKN input PCI Express 100 MHz reference clock, negative side of the differential pair.
3 AVDD33 power_in +3.3 V power supply for the analog circuit.
4 PETXP output PCI Express transmit data, positive side of the differential pair.
5 PETXN output PCI Express transmit data, negative side of the differential pair.
6 VDD10 power_in +1.05 V power supply.
7 PERXP input PCI Express receive data, positive side of the differential pair.
8 PERXN input PCI Express receive data, negative side of the differential pair.
9 VDD10 power_in +1.05 V power supply.
10 PECREQB output Open-drain PCI Express CLKREQ# signal, active low, used to request run/stop of the reference clock.
11 PONRSTB input 3.3 V Schmitt-trigger input for power-on reset, active low; when supporting wakeup from D3cold it should be pulled high with the system auxiliary supply.
12 VDD33 power_in +3.3 V power supply.
13 SPISO input SPI serial flash ROM slave output signal (3.3 V input); it should be pulled up through a pull-up resistor in all cases.
14 SPICSB output SPI serial flash ROM chip select signal; if no external serial ROM is mounted it should be pulled down through a pull-down resistor.
15 SPISCK output SPI serial flash ROM clock signal; if no external serial ROM is mounted it should be pulled down through a pull-down resistor.
16 SPISI output SPI serial flash ROM slave input signal; if no external serial ROM is mounted it should be pulled down through a pull-down resistor.
17 OCI2B input 3.3 V input over-current status for port 2, active low (0 = over-current detected, 1 = no over-current).
18 PPON2 output 3.3 V output USB port 2 power supply control, active high (0 = power supply OFF, 1 = power supply ON).
19 OCI1B input 3.3 V input over-current status for port 1, active low (0 = over-current detected, 1 = no over-current).
20 PPON1 output 3.3 V output USB port 1 power supply control, active high (0 = power supply OFF, 1 = power supply ON).
21 VDD10 power_in +1.05 V power supply.
22 VDD33 power_in +3.3 V power supply.
23 XT2 output Oscillator output; connect to the 24 MHz crystal.
24 XT1 input Oscillator input; connect to the 24 MHz crystal.
25 AVDD33 power_in +3.3 V power supply for the analog circuit.
26 RREF passive USB2 reference resistor connection.
27 IC(L) input Test pin; connect to ground.
28 U3TXDP1 output USB3.0 SuperSpeed transmit data D+ signal for port 1.
29 U3TXDN1 output USB3.0 SuperSpeed transmit data D- signal for port 1.
30 VDD10 power_in +1.05 V power supply.
31 U3RXDP1 input USB3.0 SuperSpeed receive data D+ signal for port 1.
32 U3RXDN1 input USB3.0 SuperSpeed receive data D- signal for port 1.
33 VDD10 power_in +1.05 V power supply.
34 VDD33 power_in +3.3 V power supply.
35 U2DP1 bidirectional USB2.0 D+ signal for Hi-/Full-/Low-Speed on port 1.
36 U2DM1 bidirectional USB2.0 D- signal for Hi-/Full-/Low-Speed on port 1.
37 U3TXDP2 output USB3.0 SuperSpeed transmit data D+ signal for port 2.
38 U3TXDN2 output USB3.0 SuperSpeed transmit data D- signal for port 2.
39 VDD10 power_in +1.05 V power supply.
40 U3RXDP2 input USB3.0 SuperSpeed receive data D+ signal for port 2.
41 U3RXDN2 input USB3.0 SuperSpeed receive data D- signal for port 2.
42 VDD10 power_in +1.05 V power supply.
43 VDD33 power_in +3.3 V power supply.
44 U2DP2 bidirectional USB2.0 D+ signal for Hi-/Full-/Low-Speed on port 2.
45 U2DM2 bidirectional USB2.0 D- signal for Hi-/Full-/Low-Speed on port 2.
46 SMIB output Open-drain system management interrupt signal, active low, controlled through the USB Legacy Support Control/Status register.
47 PERSTB input 3.3 V input for PCI Express PERST# signal, active low.
48 PEWAKEB output Open-drain PCI Express WAKE# signal, active low, used for remote wakeup and to request recovery of power and reference clock input.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-48(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating voltage VDD33, AVDD33 3 3.3 3.6 V 13
Operating voltage VDD10 0.9975 1.05 1.1025 V 13
High-level input voltage VIH 2 V 13
Low-level input voltage VIL 0.3 0.8 V 13
Input rise time, normal buffer Tri 0 200 ns Normal buffer 13
Input rise time, Schmitt buffer Tri 0 10 ms Schmitt buffer 13
Input fall time, normal buffer Tfi 0 200 ns Normal buffer 13
Input fall time, Schmitt buffer Tfi 0 10 ms Schmitt buffer 13
Operating ambient temperature TA -40 85 C PD720202K8-711-BAA-A 13
Power supply voltage VDD33, AVDD33 0.5 4.6 V 13
Power supply voltage VDD10 0.5 1.4 V 13
Input voltage, 3.3 V buffer VI 0.5 4.6 V VI < VDD33 + 0.5 V 13
Output voltage, 3.3 V buffer VO 0.5 4.6 V VO < VDD33 + 0.5 V 13
Output current IO 8 mA 4 mA Type 13
Storage temperature Tstg 65 125 C 13
Off-state output current IOZ 10 A VI = VDD33 or GND 14
Input leakage current II 10 A VI = VDD33 or GND 14
Low-level output voltage VOL 0.1 V IOL = 0mA 14
Output pin impedance ZHSDRV 40.5 49.5 14
High-level input voltage (floating) VIHZ 2.7 3.6 V 14
High-level input voltage (drive) VIH 2 V 14
Low-level input voltage VIL 0.8 V 14
Differential input sensitivity VDI 0.2 V 14
Differential common mode range VCM 0.8 2.5 V Includes VDI range 14
High-level output voltage (Low/Full-Speed) VOH 2.8 3.6 V RL of 14.25 k to GND 14
Low-level output voltage (Low/Full-Speed) VOL 0 0.3 V RL of 1.425 k to 3.6 V 14
SE1 output voltage VOSE1 0.8 V 14
Output signal crossover point voltage VCRS 1.3 2 V 14
Hi-Speed squelch detection threshold (differential signal) VHSSQ 100 150 mV 14
Hi-Speed disconnect detection threshold (differential signal) VHSDSC 525 625 mV 14
Hi-Speed data signaling common mode voltage range VHSCM 50 500 mV 14
Hi-Speed data signaling high VHSOH 360 440 mV 14
Chirp J level (differential signal) VCHIRPJ 700 1100 mV 14
Chirp K level (differential signal) VCHIRPK 900 500 mV 14
SPI interface pin capacitance CSPI 5 pF 15
System clock frequency tolerance FCLK -100 100 ppm Crystal 16
Clock duty cycle TDUTY 40 50 60 % 16
PCI Express reference clock rising edge rate TRISE 0.6 4 V/ns See Figure 3-5 16
PCI Express reference clock falling edge rate TFALL 0.6 4 V/ns See Figure 3-5 16
Absolute crossing point voltage VCROSS 250 550 mV See Figure 3-3 16
Absolute period (including jitter and spread spectrum) TPERIOD ABS 9.847 10.203 ns 16
Cycle to cycle jitter VCCJITTER 150 ps 16
Absolute max input voltage VMAX 1.15 V See Figure 3-3 16
Duty cycle (PCI Express reference clock) 40 60 % See Figure 3-6 16
Average clock period accuracy TPERIOD AVG 300 2800 ppm 16
Unit interval UI 199.94 200.06 ps 26
Receiver DC common mode impedance RRX-DC 18 30 26
DC differential impedance RRX-DIFF-DC 72 120 26
LFPS detect threshold VRX-LFPS-DET-DIFF-p-p 100 300 mV 26
SPISCK clock frequency 1 20 MHz 33
SPISO validate time from SPISCK falling edge tSDRVALID 25 ns 33
Full-speed rise time TFR 4 20 ns 28
Full-speed fall time TFF 4 20 ns 28
Source SE0 interval of EOP (Full-speed) TFEOPT 160 175 ns 28
Frame interval TFRAME 0.9995 1.0005 ms 28
Hi-Speed rise time (10%-90%) THSR 500 ps 29
Hi-Speed data rate THSDRAT 480.24 497.76 Mb/s 29
Time to detect a downstream facing port connect event TDCNN 2.5 2000 s 29
Time before end of reset by which hub must end downstream chirp sequence TDCHSE0 100 500 s 29

CAD (KiCad official)

  • Symbol: UPD720202K8-711-BAA-A
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: upd720202k8-711-baa-a-etched.step / upd720202k8-711-baa-a-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); upd720202k8-711-baa-a.step / upd720202k8-711-baa-a.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (43 pp, sha256 1315212fb6a9db2c, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF