component
UPD720201K8-701-BAC-A
Public Made by Adomby adom
RENESAS USB Converters, QFN-68-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUPD720201K8-701-BAC-A
RENESAS · USB Converters · QFN-68-EP(8x8)
UPD720201K8-701-BAC-A from RENESAS, in a QFN-68-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SMIB | output | System management interrupt signal, active low, open-drain output, controlled with the USB Legacy Support Control/Status register. |
| 2 | PERSTB | input | PCI Express PERST# signal, active-low 3.3 V input. |
| 3 | PEWAKEB | output | PCI Express WAKE# signal, active-low open-drain output used for remote wakeup and to request recovery of power and reference clock input. |
| 4 | PECLKP | input | PCI Express 100 MHz reference clock input (positive). |
| 5 | PECLKN | input | PCI Express 100 MHz reference clock input (negative). |
| 6 | AVDD33 | power_in | +3.3 V power supply for analog circuit. |
| 7 | PETXP | output | PCI Express transmit data+ output. |
| 8 | PETXN | output | PCI Express transmit data- output. |
| 9 | VDD10 | power_in | +1.05 V power supply. |
| 10 | PERXP | input | PCI Express receive data+ input. |
| 11 | PERXN | input | PCI Express receive data- input. |
| 12 | VDD10 | power_in | +1.05 V power supply. |
| 13 | PECREQB | output | PCI Express CLKREQ# signal, active-low open-drain output used to request run/stop of the reference clock. |
| 14 | PONRSTB | input | Active-low power-on reset 3.3 V Schmitt input; should be pulled high with system auxiliary power supply when supporting wakeup from D3cold. |
| 15 | VDD33 | power_in | +3.3 V power supply. |
| 16 | SPISO | input | SPI serial flash ROM slave output signal (3.3 V input); should be pulled up through a pull-up resistor in all cases. |
| 17 | SPICSB | output | SPI serial flash ROM chip select signal (3.3 V output); pull down through a resistor when no external serial ROM is mounted. |
| 18 | SPISCK | output | SPI serial flash ROM clock signal (3.3 V output); pull down through a resistor when no external serial ROM is mounted. |
| 19 | SPISI | output | SPI serial flash ROM slave input signal (3.3 V output); pull down through a resistor when no external serial ROM is mounted. |
| 20 | OCI4B | input | Port 4 over-current status input, active low (0: over-current detected, 1: none), 3.3 V input. |
| 21 | PPON4 | output | Port 4 USB power supply control signal, active high (0: power OFF, 1: power ON), 3.3 V output. |
| 22 | OCI3B | input | Port 3 over-current status input, active low (0: over-current detected, 1: none), 3.3 V input. |
| 23 | PPON3 | output | Port 3 USB power supply control signal, active high (0: power OFF, 1: power ON), 3.3 V output. |
| 24 | OCI2B | input | Port 2 over-current status input, active low (0: over-current detected, 1: none), 3.3 V input. |
| 25 | PPON2 | output | Port 2 USB power supply control signal, active high (0: power OFF, 1: power ON), 3.3 V output. |
| 26 | OCI1B | input | Port 1 over-current status input, active low (0: over-current detected, 1: none), 3.3 V input. |
| 27 | PPON1 | output | Port 1 USB power supply control signal, active high (0: power OFF, 1: power ON), 3.3 V output. |
| 28 | VDD10 | power_in | +1.05 V power supply. |
| 29 | VDD33 | power_in | +3.3 V power supply. |
| 30 | XT2 | output | Oscillator out; connect to 24 MHz crystal. |
| 31 | XT1 | input | Oscillator in; connect to 24 MHz crystal. |
| 32 | AVDD33 | power_in | +3.3 V power supply for analog circuit. |
| 33 | RREF | passive | Reference resistor connection (USB2 analog). |
| 34 | IC(L) | input | Test pin; connect to ground. |
| 35 | U3TXDP1 | output | Port 1 USB3.0 SuperSpeed transmit data D+ output. |
| 36 | U3TXDN1 | output | Port 1 USB3.0 SuperSpeed transmit data D- output. |
| 37 | VDD10 | power_in | +1.05 V power supply. |
| 38 | U3RXDP1 | input | Port 1 USB3.0 SuperSpeed receive data D+ input. |
| 39 | U3RXDN1 | input | Port 1 USB3.0 SuperSpeed receive data D- input. |
| 40 | VDD33 | power_in | +3.3 V power supply. |
| 41 | U2DP1 | bidirectional | Port 1 USB2.0 D+ signal for Hi-/Full-/Low-Speed. |
| 42 | U2DM1 | bidirectional | Port 1 USB2.0 D- signal for Hi-/Full-/Low-Speed. |
| 43 | VDD10 | power_in | +1.05 V power supply. |
| 44 | U3TXDP2 | output | Port 2 USB3.0 SuperSpeed transmit data D+ output. |
| 45 | U3TXDN2 | output | Port 2 USB3.0 SuperSpeed transmit data D- output. |
| 46 | VDD10 | power_in | +1.05 V power supply. |
| 47 | U3RXDP2 | input | Port 2 USB3.0 SuperSpeed receive data D+ input. |
| 48 | U3RXDN2 | input | Port 2 USB3.0 SuperSpeed receive data D- input. |
| 49 | VDD33 | power_in | +3.3 V power supply. |
| 50 | U2DP2 | bidirectional | Port 2 USB2.0 D+ signal for Hi-/Full-/Low-Speed. |
| 51 | U2DM2 | bidirectional | Port 2 USB2.0 D- signal for Hi-/Full-/Low-Speed. |
| 52 | U3TXDP3 | output | Port 3 USB3.0 SuperSpeed transmit data D+ output. |
| 53 | U3TXDN3 | output | Port 3 USB3.0 SuperSpeed transmit data D- output. |
| 54 | VDD10 | power_in | +1.05 V power supply. |
| 55 | U3RXDP3 | input | Port 3 USB3.0 SuperSpeed receive data D+ input. |
| 56 | U3RXDN3 | input | Port 3 USB3.0 SuperSpeed receive data D- input. |
| 57 | VDD33 | power_in | +3.3 V power supply. |
| 58 | U2DP3 | bidirectional | Port 3 USB2.0 D+ signal for Hi-/Full-/Low-Speed. |
| 59 | U2DM3 | bidirectional | Port 3 USB2.0 D- signal for Hi-/Full-/Low-Speed. |
| 60 | VDD10 | power_in | +1.05 V power supply. |
| 61 | U3TXDP4 | output | Port 4 USB3.0 SuperSpeed transmit data D+ output. |
| 62 | U3TXDN4 | output | Port 4 USB3.0 SuperSpeed transmit data D- output. |
| 63 | VDD10 | power_in | +1.05 V power supply. |
| 64 | U3RXDP4 | input | Port 4 USB3.0 SuperSpeed receive data D+ input. |
| 65 | U3RXDN4 | input | Port 4 USB3.0 SuperSpeed receive data D- input. |
| 66 | VDD33 | power_in | +3.3 V power supply. |
| 67 | U2DP4 | bidirectional | Port 4 USB2.0 D+ signal for Hi-/Full-/Low-Speed. |
| 68 | U2DM4 | bidirectional | Port 4 USB2.0 D- signal for Hi-/Full-/Low-Speed. |
| 69 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | QFN-68-EP(8x8) |
| Category | Interface |
| Pins | 69 |
CAD (KiCad official)
- Symbol:
UPD720201K8-701-BAC-A - Footprint:
Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm - 3D model: QFN-68-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
upd720201k8-701-bac-a-etched.step/upd720201k8-701-bac-a-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);upd720201k8-701-bac-a.step/upd720201k8-701-bac-a.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (43 pp, sha256
69a66517a20086c1, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).