component
ULN2003ADTR
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XBLW Darlington Transistor Arrays, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# ULN2003ADTR++**XBLW** · Darlington Transistor Arrays · SOP-16++ULN2003ADTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1B | input | Channel 1 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 2 | 2B | input | Channel 2 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 3 | 3B | input | Channel 3 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 4 | 4B | input | Channel 4 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 5 | 5B | input | Channel 5 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 6 | 6B | input | Channel 6 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 7 | 7B | input | Channel 7 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V. |+| 8 | E | power_in | Common emitter ground return for all seven Darlington channels; connect to system GND. |+| 9 | COM | power_in | Common anode of freewheeling (suppression) diodes; connect to inductive-load supply rail, max 60 V. |+| 10 | 7C | output | Channel 7 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 11 | 6C | output | Channel 6 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 12 | 5C | output | Channel 5 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 13 | 4C | output | Channel 4 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 14 | 3C | output | Channel 3 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 15 | 2C | output | Channel 2 open-collector output; sinks up to 500 mA at VCE up to 60 V. |+| 16 | 1C | output | Channel 1 open-collector output; sinks up to 500 mA at VCE up to 60 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | XBLW |+| Package | SOP-16 |+| Category | Transistors/Thyristors |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `ULN2003ADTR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `uln2003adtr-etched.step` / `uln2003adtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `uln2003adtr.step` / `uln2003adtr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [XBLW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8563440617108619264) (11 pp, sha256 `4664a1830f57e6c2`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/uln2003adtr-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "uln2003adtr",+ "version": "0.1.0",+ "type": "component",+ "description": "XBLW Darlington Transistor Arrays, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "transistors-thyristors",+ "uln2003adtr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "uln2003adtr.kicad_sym",+ "uln2003adtr.kicad_mod",+ "uln2003adtr.glb",+ "uln2003adtr.step",+ "uln2003adtr.lbr",+ "docs/hero.png",+ "docs/uln2003adtr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "ULN2003ADTR",+ "manufacturer": "XBLW",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Transistors/Thyristors",+ "subcategory": "Darlington Transistor Arrays",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8563440617108619264",+ "parts": {+ "symbol": "uln2003adtr.kicad_sym",+ "footprint": "uln2003adtr.kicad_mod",+ "model_3d": "uln2003adtr-etched.glb",+ "model_3d_plain": "uln2003adtr.glb",+ "model_3d_step": "uln2003adtr-etched.step",+ "model_3d_step_plain": "uln2003adtr.step",+ "lbr": "uln2003adtr.lbr"+ },+ "distributor_links": {+ "lcsc": "C18723566"+ },+ "pins": [+ {+ "number": "1",+ "name": "1B",+ "type": "input",+ "description": "Channel 1 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "2",+ "name": "2B",+ "type": "input",+ "description": "Channel 2 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "3",+ "name": "3B",+ "type": "input",+ "description": "Channel 3 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "4",+ "name": "4B",+ "type": "input",+ "description": "Channel 4 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "5",+ "name": "5B",+ "type": "input",+ "description": "Channel 5 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "6",+ "name": "6B",+ "type": "input",+ "description": "Channel 6 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "7",+ "name": "7B",+ "type": "input",+ "description": "Channel 7 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V."+ },+ {+ "number": "8",+ "name": "E",+ "type": "power_in",+ "description": "Common emitter ground return for all seven Darlington channels; connect to system GND."+ },+ {+ "number": "9",+ "name": "COM",+ "type": "power_in",+ "description": "Common anode of freewheeling (suppression) diodes; connect to inductive-load supply rail, max 60 V."+ },+ {+ "number": "10",+ "name": "7C",+ "type": "output",+ "description": "Channel 7 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "11",+ "name": "6C",+ "type": "output",+ "description": "Channel 6 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "12",+ "name": "5C",+ "type": "output",+ "description": "Channel 5 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "13",+ "name": "4C",+ "type": "output",+ "description": "Channel 4 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "14",+ "name": "3C",+ "type": "output",+ "description": "Channel 3 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "15",+ "name": "2C",+ "type": "output",+ "description": "Channel 2 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ },+ {+ "number": "16",+ "name": "1C",+ "type": "output",+ "description": "Channel 1 open-collector output; sinks up to 500 mA at VCE up to 60 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 11,+ "cost_usd": 0.2549,+ "at": "2026-09-18T02:49:07"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8563440617108619264",+ "pages": 11,+ "sha256": "4664a1830f57e6c2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}