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ULN2003ADTR

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XBLW Darlington Transistor Arrays, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ULN2003ADTR

XBLW · Darlington Transistor Arrays · SOP-16

ULN2003ADTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Channel 1 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
2 2B input Channel 2 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
3 3B input Channel 3 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
4 4B input Channel 4 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
5 5B input Channel 5 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
6 6B input Channel 6 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
7 7B input Channel 7 base input; logic input compatible with TTL/CMOS, input voltage range 0-24 V.
8 E power_in Common emitter ground return for all seven Darlington channels; connect to system GND.
9 COM power_in Common anode of freewheeling (suppression) diodes; connect to inductive-load supply rail, max 60 V.
10 7C output Channel 7 open-collector output; sinks up to 500 mA at VCE up to 60 V.
11 6C output Channel 6 open-collector output; sinks up to 500 mA at VCE up to 60 V.
12 5C output Channel 5 open-collector output; sinks up to 500 mA at VCE up to 60 V.
13 4C output Channel 4 open-collector output; sinks up to 500 mA at VCE up to 60 V.
14 3C output Channel 3 open-collector output; sinks up to 500 mA at VCE up to 60 V.
15 2C output Channel 2 open-collector output; sinks up to 500 mA at VCE up to 60 V.
16 1C output Channel 1 open-collector output; sinks up to 500 mA at VCE up to 60 V.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-16
Category Transistors/Thyristors
Pins 16

CAD (KiCad official)

  • Symbol: ULN2003ADTR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: uln2003adtr-etched.step / uln2003adtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uln2003adtr.step / uln2003adtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (11 pp, sha256 4664a1830f57e6c2, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF