component

UJ3C065080K3S

Public Made by Adom

by adom

Qorvo MOSFETs, TO-247-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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UJ3C065080K3S

Qorvo · MOSFETs · TO-247-3

UJ3C065080K3S from Qorvo, in a TO-247-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate terminal of the cascode SiC FET, with a maximum gate-source DC rating of -25 V to +25 V and switching tests run at VGS = -5 V / +15 V.
2 D passive Drain terminal of the SiC FET, rated for a drain-source voltage of 650 V and a maximum drain current of 31 A in the maximum ratings table.
3 S passive Source terminal of the cascode device, which is the reference for the gate drive; the datasheet gives no separate electrical limit for this pin.

Key specifications

Parameter Value
Manufacturer Qorvo
Package TO-247-3
Category Triode/MOS Tube/Transistor
Pins 3

CAD (KiCad official)

  • Symbol: UJ3C065080K3S
  • Footprint: Package_TO_SOT_THT:TO-247-3_Vertical
  • 3D model: TO-247-3 (KiCad packages3D, STEP)
  • 3D model files: uj3c065080k3s-etched.step / uj3c065080k3s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uj3c065080k3s.step / uj3c065080k3s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Qorvo datasheet (10 pp, sha256 02858732a147ede6, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF