# UFS08A2.8L04

**Brightking** · ESD And Surge Protection (TVS/ESD) · SOIC-8

UFS08A2.8L04 from Brightking, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IO1 | passive | I/O line 1 ESD clamp, 2.8V working voltage, to be connected to pin 8 per the recommended configuration. |
| 2 | IO2 | passive | I/O line 2 ESD clamp, 2.8V working voltage, to be connected to pin 7 per the recommended configuration. |
| 3 | IO3 | passive | I/O line 3 ESD clamp, 2.8V working voltage, to be connected to pin 6 per the recommended configuration. |
| 4 | IO4 | passive | I/O line 4 ESD clamp, 2.8V working voltage, to be connected to pin 5 per the recommended configuration. |
| 5 | IO4 | passive | I/O line 4 ESD clamp, 2.8V working voltage, to be connected to pin 4 per the recommended configuration. |
| 6 | IO3 | passive | I/O line 3 ESD clamp, 2.8V working voltage, to be connected to pin 3 per the recommended configuration. |
| 7 | IO2 | passive | I/O line 2 ESD clamp, 2.8V working voltage, to be connected to pin 2 per the recommended configuration. |
| 8 | IO1 | passive | I/O line 1 ESD clamp, 2.8V working voltage, to be connected to pin 1 per the recommended configuration. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Brightking |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Peak pulse power (tp=8/20μs waveform) | PPP |  |  | 600 | W | tp=8/20μs waveform | 1 |
| ESD voltage (Contact discharge) | VESD | -8 |  | 8 | kV | Contact discharge | 1 |
| ESD voltage (Air discharge) | VESD | -15 |  | 15 | kV | Air discharge | 1 |
| Storage & operating temperature range | TSTG ,TJ | -55 |  | 150 | ℃ |  | 1 |
| Reverse stand-off voltage | VRWM |  |  | 2.8 | V |  | 2 |
| Reverse breakdown voltage | VBR | 3 |  |  | V | IBR=1mA | 2 |
| Reverse leakage current | IR |  |  | 5 | μA | VR=2.8V, each I/O pin | 2 |
| Clamping voltage (tp=8/20μs) | VC |  |  | 8.5 | V | IPP=5A | 2 |
| Peak pulse current (tp=8/20μs) | IPP |  |  | 24 | A | tp=8/20μs | 2 |
| Off state junction capacitance, I/O pins to GND | CJ |  |  | 3 | pF | 0Vdc, f=1MHz, between I/O pins and GND | 2 |
| Off state junction capacitance, line to line | CJ |  |  | 6 | pF | 0Vdc, f=1MHz, line to line, two I/O pins connected together on each line (Note) | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | ● Lead Free/RoHS compliant ● Solder reflow temperature: Pure Tin-Sn, 260~270℃ | 1 |

## CAD (KiCad official)

- Symbol: `UFS08A2.8L04`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ufs08a2-8l04-etched.step` / `ufs08a2-8l04-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ufs08a2-8l04.step` / `ufs08a2-8l04.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Brightking datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175972089466880) (5 pp, sha256 `914947f9f6438308`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ufs08a2-8l04-datasheet.pdf)