component
UCD9090QRGZRQ1
Public Made by Adomby adom
Texas Instruments Monitors & Reset Circuits, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCD9090QRGZRQ1
Texas Instruments · Monitors & Reset Circuits · VQFN-48-EP(7x7)
UCD9090QRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MON1 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 2 | MON2 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 3 | RESET | input | Active-low device reset input; hold low for at least 2 µs to reset the device. |
| 4 | GPIO1 | bidirectional | General-purpose discrete I/O. |
| 5 | GPIO2 | bidirectional | General-purpose discrete I/O. |
| 6 | GPIO3 | bidirectional | General-purpose discrete I/O. |
| 7 | GPIO4 | bidirectional | General-purpose discrete I/O. |
| 8 | PMBUS_CLK | bidirectional | PMBus clock; must have a pullup to 3.3 V. |
| 9 | PMBUS_DATA | bidirectional | PMBus data; must have a pullup to 3.3 V. |
| 10 | FPWM1/GPIO5 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 11 | FPWM2/GPIO6 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 12 | FPWM3/GPIO7 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 13 | FPWM4/GPIO8 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 14 | FPWM5/GPIO9 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 15 | FPWM6/GPIO10 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 16 | FPWM7/GPIO11 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 17 | FPWM8/GPIO12 | bidirectional | PWM output (15.259 kHz to 125 MHz) or GPIO. |
| 18 | GPIO13 | bidirectional | General-purpose discrete I/O. |
| 19 | PMBUS_ALERT | output | PMBus alert, active-low open-drain output; must have a pullup to 3.3 V. |
| 20 | PMBUS_CNTRL | input | PMBus control input. |
| 21 | GPIO14 | bidirectional | General-purpose discrete I/O. |
| 22 | PWM1/GPI1 | input | PWM output (0.93 Hz to 7.8125 MHz) or general-purpose input. |
| 23 | PWM2/GPI2 | input | PWM output (0.93 Hz to 7.8125 MHz) or general-purpose input. |
| 24 | GPIO15 | bidirectional | General-purpose discrete I/O. |
| 25 | GPIO16 | bidirectional | General-purpose discrete I/O. |
| 26 | GPIO17 | bidirectional | General-purpose discrete I/O. |
| 27 | TCK/GPIO18 | bidirectional | JTAG test clock or GPIO. |
| 28 | TDO/GPIO19 | bidirectional | JTAG test data out or GPIO. |
| 29 | TDI/GPIO20 | bidirectional | JTAG test data in (tie to Vdd with a 10-kΩ resistor) or GPIO. |
| 30 | TMS/GPIO21 | bidirectional | JTAG test mode select (tie to Vdd with a 10-kΩ resistor) or GPIO. |
| 31 | TRST | input | JTAG test reset; tie to ground with a 10-kΩ resistor. |
| 32 | DVSS | power_in | Digital ground. |
| 33 | V33D | power_in | Digital core 3.3-V supply; decouple with 0.1 µF in parallel with 4.7 µF. |
| 34 | V33A | power_in | Analog 3.3-V supply; decouple with 0.1 µF in parallel with 4.7 µF. |
| 35 | BPCAP | passive | 1.8-V bypass capacitor pin; use 0.1 µF in parallel with 0.01 µF. |
| 36 | AVSS1 | power_in | Analog ground. |
| 37 | MON11 | input | Analog monitor input with a 0.2 V to 2.5 V range. |
| 38 | MON3 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 39 | MON4 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 40 | MON5 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 41 | MON6 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 42 | MON7 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 43 | PMBUS_ADDR1 | input | PMBus analog address input, most-significant address bit. |
| 44 | PMBUS_ADDR0 | input | PMBus analog address input, least-significant address bit. |
| 45 | MON8 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 46 | MON9 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 47 | AVSS2 | power_in | Analog ground. |
| 48 | MON10 | input | Analog monitor input with a 0 V to 2.5 V range. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Power Supply Chip |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage applied at V33D to DVSS | V33D | -0.3 | 3.8 | V | 2 | ||
| Voltage applied at V33A to AVSS | V33A | -0.3 | 3.8 | V | 2 | ||
| Voltage applied to any other pin | -0.3 | V | max is V33A + 0.3 V; referenced to VSS | 2 | |||
| Storage temperature | Tstg | -40 | 150 | °C | 2 | ||
| ESD rating HBM | 2.5 | kV | Human-body model | 2 | |||
| ESD rating CDM | 750 | V | Charged-device model | 2 | |||
| Supply voltage during operation | V33D, V33DIO, V33A | 3 | 3.3 | 3.6 | V | 3 | |
| Operating free-air temperature range | TA | -40 | 125 | °C | 3 | ||
| Junction-to-ambient thermal resistance | θJA | 25 | °C/W | RGZ (48 pins) | 2 | ||
| Junction-to-case (top) thermal resistance | θJCtop | 8.9 | °C/W | RGZ (48 pins) | 2 | ||
| Junction-to-board thermal resistance | θJB | 5.5 | °C/W | RGZ (48 pins) | 2 | ||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | RGZ (48 pins) | 2 | ||
| Junction-to-board characterization parameter | ψJB | 1.5 | °C/W | RGZ (48 pins) | 2 | ||
| Junction-to-case (bottom) thermal resistance | θJCbot | 1.7 | °C/W | RGZ (48 pins) | 2 | ||
| MON1-MON10 input voltage range | VMON | 0 | 2.5 | V | MON1-MON10 | 3 | |
| MON11 input voltage range | VMON | 0.2 | 2.5 | V | MON11 | 3 | |
| ADC integral nonlinearity | INL | -4 | 4 | LSB | 3 | ||
| ADC differential nonlinearity | DNL | -2 | 2 | LSB | 3 | ||
| Input leakage current | Ilkg | 100 | nA | 3 V applied to pin | 3 | ||
| Input offset current | IOFFSET | -5 | 5 | μA | 1-kΩ source impedance | 3 | |
| Input impedance MON1-MON10 | RIN | 8 | MΩ | MON1-MON10, ground reference | 3 | ||
| Input impedance MON11 | RIN | 0.5 | 1.5 | 3 | MΩ | MON11, ground reference | 3 |
| ADC internal reference accuracy 0°C to 125°C | VREF | -0.5 | 0.5 | % | ADC 2.5 V, internal reference accuracy 0°C to 125°C | 3 | |
| ADC internal reference accuracy -40°C to 125°C | VREF | -1 | 1 | % | ADC 2.5 V, internal reference accuracy -40°C to 125°C | 3 | |
| Bias current for PMBus Addr pins | IBIAS | 9 | 11 | μA | 3 | ||
| Low-level output voltage | VOL | 0.3 | V | IOL = 6 mA, V33DIO = 3 V; max is Dgnd + 0.3 V | 4 | ||
| High-level input voltage | VIH | 2.1 | 3.6 | V | V33DIO = 3 V | 4 | |
| Low-level input voltage | VIL | 1.4 | V | V33DIO = 3.5 V | 4 | ||
| MARGINING-PWM frequency FPWM1-8 | fPWM_FREQ | 15.26 | 125000 | kHz | FPWM1-8 | 4 | |
| MARGINING-PWM frequency PWM1-2 | fPWM_FREQ | 0.001 | 7800 | kHz | PWM1-2 | 4 | |
| MARGINING-PWM duty-cycle range | DUTYPWM | 0 | 100 | % | 4 | ||
| Minimum VDD slew rate | VDDSlew | 0.25 | V/ms | VDD slew rate between 2.3 V and 2.9 V | 4 | ||
| Supply voltage at which device comes out of reset | VRESET | 2.4 | V | For power-on reset (POR) | 4 | ||
| Low-pulse duration needed at RESET pin | tRESET | 2 | μs | To reset device during normal operation | 4 | ||
| Internal oscillator frequency | f(PCLK) | 240 | 250 | 260 | MHz | TA = 125°C, TA = 25°C | 4 |
| Retention of configuration parameters | tretention | 100 | Years | TJ = 25°C | 4 | ||
| Number of nonvolatile erase-and-write cycles | Write_Cycles | 20 | K cycles | TJ = 25°C | 4 | ||
| SMBus or PMBus operating frequency | f(SMB) | 10 | 400 | kHz | Slave mode, SMBC 50% duty cycle | 5 | |
| I2C operating frequency | f(I2C) | 10 | 400 | kHz | Slave mode, SCL 50% duty cycle | 5 | |
| Bus free time between start and stop | t(BUF) | 4.7 | μs | 5 | |||
| Hold time after (repeated) start | t(HD:STA) | 0.26 | μs | 5 | |||
| Repeated-start setup time | t(SU:STA) | 0.26 | μs | 5 | |||
| Stop setup time | t(SU:STO) | 0.26 | μs | 5 | |||
| Data hold time | t(HD:DAT) | 0 | ns | Receive mode | 5 | ||
| Data setup time | t(SU:DAT) | 50 | ns | 5 | |||
| Error signal or detect | t(TIMEOUT) | 35 | ms | See (1) | 5 | ||
| Clock low period | t(LOW) | 0.5 | μs | 5 | |||
| Clock high period | t(HIGH) | 0.26 | 50 | μs | See (2) | 5 | |
| Cumulative clock-low slave-extend time | t(LOW:SEXT) | 25 | ms | See (3) | 5 | ||
| Clock or data fall time | tf | 120 | ns | See (4) | 5 | ||
| Clock or data rise time | tr | 120 | ns | See (5) | 5 | ||
| Supply current IV33A | IV33A | 8 | mA | VV33A = 3.3 V | 3 | ||
| Supply current IV33DIO | IV33DIO | 2 | mA | VV33DIO = 3.3 V | 3 | ||
| Supply current IV33D | IV33D | 40 | mA | VV33D = 3.3 V | 3 | ||
| Supply current IV33D during flash write | IV33D | 50 | mA | VV33D = 3.3 V, storing configuration parameters in flash memory | 3 | ||
| Input capacitance | CIN | 10 | pF | 3 | |||
| ADC sample period | tCONVERT | 400 | μs | 12 voltages sampled, 3.89 μs/sample | 3 | ||
| Voltage, open pin | VADDR_OPEN | 2.26 | V | PMBUS_ADDR0, PMBUS_ADDR1 open | 3 | ||
| Voltage, shorted pin | VADDR_SHORT | 0.124 | V | PMBUS_ADDR0, PMBUS_ADDR1 short to ground | 3 |
CAD (KiCad official)
- Symbol:
UCD9090QRGZRQ1 - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ucd9090qrgzrq1-etched.step/ucd9090qrgzrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucd9090qrgzrq1.step/ucd9090qrgzrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (50 pp, sha256
35515560e756455d, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).