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UCD90120RGCR

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Texas Instruments Supervisor And Reset ICs, VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ucd90120rgcrfactory-2.0.0extractor-text

Verified UCD90120RGCR

by Ray · last 5 Nov 2026 · 1 record · files match
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Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: UCD90120RGCR · VQFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 42-page datasheet
  • ✓distributor: lcsc C2070254, digikey UCD90120RGCR-ND, mouser 595-UCD90120RGCR
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-p4uuf8dn/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ucd90120rgcr.kicad_sym✓ ucd90120rgcr.kicad_mod✓ ucd90120rgcr.step
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Contents

README

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UCD90120RGCR

Texas Instruments · Supervisor And Reset ICs · VQFN-64-EP(9x9)

UCD90120RGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MON1 input Analog monitor input with a 0 V to 2.5 V range.
2 MON2 input Analog monitor input with a 0 V to 2.5 V range.
3 MON3 input Analog monitor input with a 0 V to 2.5 V range.
4 MON4 input Analog monitor input with a 0 V to 2.5 V range.
5 MON5 input Analog monitor input with a 0 V to 2.5 V range.
6 MON6 input Analog monitor input with a 0 V to 2.5 V range.
7 V33DIO1 power_in Digital I/O 3.3 V supply, 3.0 V to 3.6 V operating range.
8 DVSS1 power_in Digital ground.
9 nRESET input Active-low device reset input that must be held low for at least 2 µs to reset the device.
10 TRCK output JTAG test return clock output.
11 GPIO1 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
12 GPIO2 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
13 GPIO3 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
14 GPIO4 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
15 PMBUS_CLK bidirectional PMBus clock that must have a pull-up to 3.3 V.
16 PMBUS_DATA bidirectional PMBus data that must have a pull-up to 3.3 V.
17 FPWM1/GPIO5 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
18 FPWM2/GPIO6 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
19 FPWM3/GPIO7 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
20 FPWM4/GPIO8 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
21 FPWM5/GPIO9 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
22 FPWM6/GPIO10 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
23 FPWM7/GPIO11 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
24 FPWM8/GPIO12 bidirectional PWM output from 15.259 kHz to 125 MHz, or general-purpose I/O.
25 GPIO13 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
26 DVSS2 power_in Digital ground.
27 PMBALERT# output Active-low PMBus alert open-drain output that must have a pull-up to 3.3 V.
28 PMBUS_CNTRL input PMBus control input.
29 GPIO14 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
30 GPIO15 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
31 PWM1/GPI1 input Fixed 10 kHz PWM output or general-purpose input.
32 PWM2/GPI2 input Fixed 1 kHz PWM output or general-purpose input.
33 GPIO16 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
34 GPIO17 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
35 GPIO18 bidirectional General-purpose discrete I/O that can be used as an enable, reset or power good signal.
36 TCK/GPIO19 bidirectional JTAG test clock or general-purpose I/O.
37 TDO/GPIO20 bidirectional JTAG test data out or general-purpose I/O.
38 TDI/GPIO21 bidirectional JTAG test data in or general-purpose I/O; tie to Vdd with a 10k resistor.
39 TMS/GPIO22 bidirectional JTAG test mode select or general-purpose I/O; tie to Vdd with a 10k resistor.
40 nTRST input JTAG test reset that must be tied to ground with a 10k resistor.
41 PWM4/GPI4 input PWM output from 0.93 Hz to 7.8125 MHz, or general-purpose input.
42 PWM3/GPI3 input PWM output from 0.93 Hz to 7.8125 MHz, or general-purpose input.
43 DVSS3 power_in Digital ground.
44 V33DIO2 power_in Digital I/O 3.3 V supply, 3.0 V to 3.6 V operating range.
45 V33D power_in Digital core 3.3 V supply, 3.0 V to 3.6 V operating range.
46 V33A power_in Analog 3.3 V supply, 3.0 V to 3.6 V operating range.
47 BPCAP passive 1.8 V bypass capacitor pin that must be tied to analog ground through a 0.1 µF capacitor.
48 AVSS2 power_in Analog ground.
49 AVSS1 power_in Analog ground.
50 MON10 input Analog monitor input with a 0.2 V to 2.5 V range.
51 NC1 unconnected Not connected.
52 MON11 input Analog monitor input with a 0.2 V to 2.5 V range.
53 NC2 unconnected Not connected.
54 MON12 input Analog monitor input with a 0.2 V to 2.5 V range.
55 NC3 unconnected Not connected.
56 MON13 input Analog monitor input with a 0.2 V to 2.5 V range.
57 NC4 unconnected Not connected.
58 V33FB passive 3.3 V linear regulator feedback connection.
59 MON7 input Analog monitor input with a 0 V to 2.5 V range.
60 PMBUS_ADDR1 input PMBus analog address input for the most significant address bit.
61 PMBUS_ADDR0 input PMBus analog address input for the least significant address bit.
62 MON8 input Analog monitor input with a 0 V to 2.5 V range.
63 MON9 input Analog monitor input with a 0 V to 2.5 V range.
64 AVSS3 power_in Analog ground.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category Power Management (PMIC)
Pins 65

CAD (KiCad official)

  • Symbol: UCD90120RGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ucd90120rgcr-etched.step / ucd90120rgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucd90120rgcr.step / ucd90120rgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 67ec9288a91076f9, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF